"Linear Equation Solver using CMOS Technology" - Microelectronic ...

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ContentsAcknowledgements ............................................................................................................................. 2Abstract ............................................................................................................................................... 3Contents .............................................................................................................................................. 4List of Figures ....................................................................................................................................... 61 Introduction ................................................................................................................................. 82 Overview of the Digital Linear Equation Solver Hardware ........................................................ 102.1. Digital Linear Equation Solver in Small Scale (4 unknowns) .................................................. 112.1.1. Initial Design .................................................................................................................... 112.1.2. Revised Design .................................................................................................................. 132.1.3. Final Design ....................................................................................................................... 152.2. Digital Linear Equation Solver with 8 unknowns ................................................................... 182.2.1. Final Design ...................................................................................................................... 183 Digital Linear Equation Solver Hardware Implementation ....................................................... 203.1. Digital Linear Equation Solver with 4 unknowns .................................................................. 203.1.1. Initial Design ..................................................................................................................... 203.1.2. Revised Design .................................................................................................................. 213.1.3. Final Design ....................................................................................................................... 243.2. Digital Linear Equation Solver with 8 unknowns .................................................................. 243.2.1. Final Design ....................................................................................................................... 244 Implementation Results ........................................................................................................... 274.1. Digital Linear Equation Solver with 4 unknowns .................................................................. 274.1.1. Initial Design ..................................................................................................................... 274.1.2. Revised Design .................................................................................................................. 284.1.3. Final Design ....................................................................................................................... 314.2. Digital Linear Equation Solver with 8 unknowns .................................................................. 354.2.1. Final Design ....................................................................................................................... 355 Further Improvements and Comments ..................................................................................... 436 Conclusions ................................................................................................................................ 447 References ................................................................................................................................. 45Appendices ........................................................................................................................................ 46A1 Basic Building Blocks of the Solver .............................................................................................. 46A1.1. Inverter Cell .............................................................................................................................. 46A1.2. AND Cell ................................................................................................................................... 474
A1.3. XOR Cell .................................................................................................................................... 48A1.4. DLATCH Cell .............................................................................................................................. 49A1.5. DFF Cell ..................................................................................................................................... 50A1.6. Input Buffers ............................................................................................................................ 51A1.7. Simulation Setups..................................................................................................................... 52A1.7.1. Simulation Setup for the Initial Solver (4 unknowns) ........................................................... 52A1.7.2. Simulation Setup for the Revised Solver (4 unknowns) ........................................................ 53A1.7.3. Simulation Setup for the Final Solver (8 unknowns) ............................................................. 54A2 VHDL Codes ................................................................................................................................. 55A2.1. Initial Solver (4 unknowns) ............................................................................................... 55A2.1.1. GenSolver4_noDFF.vhd ............................................................................................... 55A2.2. Revised Solver (4 unknowns) ............................................................................................ 56A2.2.1. GenSolver4.vhd ............................................................................................................ 56A2.2.2. GenSolver4_tb.vhd ....................................................................................................... 59A2.3. Final Solver (4 unknowns)................................................................................................. 59A2.3.1. CK_prioritizer.vhd ............................................................................................................. 59A3 MATLAB codes.............................................................................................................................. 59A3.1. All_input_matrices_4x4.m................................................................................................ 59A3.2. Rand_GenTestcase.m ....................................................................................................... 615
Page 2: AcknowledgementsI would like to tha
Page 7 and 8: Figure 44. Schematic of DFF gate ..
Page 9 and 10: Figure 2. Schematic of three LSFRs
Page 11 and 12: 2.1. Digital Linear Equation Solver
Page 13 and 14: 2.1.2. Revised DesignIn order to pr
Page 15 and 16: 2.1.3. Final DesignThe timing of th
Page 17 and 18: Figure 7. Schematic of the Final So
Page 19 and 20: After verifying the correct operati
Page 21 and 22: 3.1.2. Revised DesignAs mentioned b
Page 23 and 24: Figure 11. CADENCE Schematic of Rev
Page 25 and 26: Figure 12. CADENCE Schematic of the
Page 27 and 28: 4 Implementation Results4.1. Digita
Page 29 and 30: Figure 15. MODELSIM Output waveform
Page 31 and 32: Figure 19. CADENCE Output waveforms
Page 39 and 40: Figure 32. Output waveforms_6 for t
Page 41 and 42: Figure 36. Output waveforms_8 for t
Page 43 and 44: 5 Further Improvements and Comments
Page 45 and 46: 7 References1 - "Encryption" , Data
Page 47 and 48: A1.2. AND CellFigure 40. Schematic
Page 49 and 50: A1.4. DLATCH CellFigure 43. Schemat
Page 51 and 52: A1.6. Input BuffersFigure 45. Schem
Page 53 and 54:
A1.7.2. Simulation Setup for the Re
Page 55 and 56:
A2 VHDL CodesA2.1.Initial Solver (4
Page 57 and 58:
Xout (2)
Page 59 and 60:
A2.2.2.GenSolver4_tb.vhdAs mentione
Page 61 and 62:
endcountfclose(fid);endelsextxt=[xt
Page 63:
if(K==N) %if you cannot find a 1 in
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