ABCs of ADCs - Analog-to-Digital Converter Basics (PDF)

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Full-Scale (Offset) Error111ACTUALFull-ScaleError110OUTPUT CODE101100011010IDEAL0010001/8 1/4 3/8 1/2 5/8 3/4 7/8 FSANALOG INPUT (V)10NCG 9/99In an ideal A/D converter, the output code transition to full scale just barely occurs when theinput voltage equals G * V REF * (2 n - 1.5) / 2 n , where “G” is the gain of the converter (usually“1”), V REF is the ADC reference voltage and “n” is the resolution (number of output bits) of theADC.In an actual ADC the full-scale analog input causing this transition may differ somewhat fromthis ideal value. Full Scale Error is the error in the actual full-scale output transition point fromthe ideal value. Part of this error will be due to offset voltage and the rest will be due to anerror in the slope of the transfer function. Full Scale Error may be expressed in LSBs or as apercentage of the full-scale voltage.Full Scale Error is sometimes called Full Scale Offset Error and is expressed in LSBs, Volts oras a percentage of ideal full scale input.Top Offset is yet another type of full scale error, defined as the difference between the positivereference voltage and the input voltage that just causes the output code to transition to fullscale plus 1.5 LSB, or V FS :E OT = V FT +1.5 LSB - V REF = V FS – V REFwhere E OT is the Top Offset voltageV FT is the input voltage causing the full-scale transitionV REF is the ADC reference voltageV FS is 1.5 LSB above V FT .Top Offset is a very unusual specification.ABCs of ADCs - Rev 3, June 2006Authored by: Nicholas “Nick” Gray10Copyright © 2003, 2004, 2006 National SemiconductorCorporationAll rights reserved
Gain Error (Full-Scale GainError)Gain Error111ACTUALOUTPUT CODE110101100011010SHIFTED ACTUALIDEAL0010001/8 1/4 3/8 1/2 5/8 3/4 7/8 FSANALOG INPUT (V)11NCG 9/99Gain Error, or Full-Scale Gain Error, is a deviation from the ideal slope of the transfer function.It is the same as full-scale error with the offset error subtracted. If we shift the actual transfercurve so that zero scale offset error becomes zero, the difference between the actual andideal transitions to full scale is the Gain Error.Full Scale Error is expressed in LSBs, or as a percentage of the ideal full-scale voltage.ABCs of ADCs - Rev 3, June 2006Authored by: Nicholas “Nick” Gray11Copyright © 2003, 2004, 2006 National SemiconductorCorporationAll rights reserved
Page 1 and 2: ABCs of ADCsAnalog-to-Digital Conve
Page 3 and 4: What Is an ADC?• Mixed-Signal Dev
Page 5 and 6: Least Significant Bit (LSB)andMost
Page 7 and 8: Quantization Error111Digital Output
Page 9: Offset Error111OUTPUT CODE110101100
Page 13 and 14: DNL1111101010.3 LSB;DNL = -0.7Ideal
Page 15 and 16: Integral Non-Linearity (INL)orInteg
Page 17 and 18: Total Unadjusted Error101OUTPUT COD
Page 19 and 20: THD - Total HarmonicDistortionAnalo
Page 21 and 22: 1Signal-to-Noise and Distortion(SIN
Page 23 and 24: ENOB - Effective Number OfBits• E
Page 25 and 26: Input Dynamic RangeDynamic Range is
Page 27 and 28: Sources of Noiseand DistortionABCs
Page 29 and 30: Inadequate Supply Bypassing• Nois
Page 31 and 32: V A - DR Decoupling• ADC Outputs
Page 33 and 34: Output to Input Coupling• Output
Page 35 and 36: Noisy Components/Circuitry• ADC I
Page 37 and 38: Clock Noise• Clock Can Add Noise
Page 39 and 40: Common Design Mistakes• Inadequat
Page 41 and 42: Noisy Components/Circuitry• ADC I
Page 43 and 44: Better Conditioning Circuitry22 220
Page 45 and 46: Resistor Pack Danger500*V REF +V RE
Page 47 and 48: Clock Noise• Clock Can Add Noise
Page 49 and 50: Excessive Clock Jitter (cont’d)No
Page 51 and 52: Treating the Clock LineAs a Trace
Page 53 and 54: A Better Reference CircuitLM4040-4.
Page 55 and 56: High Speed ADCs FromNational: 10-bi
Page 57 and 58: High Speed ADCs FromNational: 14 &
Page 59 and 60: Other General Purpose ADCsFrom Nati
Page 61 and 62:
ADC Web Site• Site: www.national.
Page 63 and 64:
Absolute Maximum Ratings - Voltages
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ABCs of ADCs - Analog-to-Digital Converter Basics (PDF)

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