ABCs of ADCs - Analog-to-Digital Converter Basics (PDF)

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Quantization Noise• Quantization Produces Noise• Quantization Noise Is Inversely• Inversely Proportional to ADC Resolution36The fact that the input signal is quantized means that noise is added to it. Quantization noise isless with higher resolution as the input range is divided into a greater number of smallerranges.ABCs of ADCs - Rev 3, June 2006Authored by: Nicholas “Nick” Gray36Copyright © 2003, 2004, 2006 National SemiconductorCorporationAll rights reserved
Clock Noise• Clock Can Add Noise• Clock Can Be Noisy, Exhibiting Jitter– For Ideal SNR, Max Jitter = 1/(2 (n+1) π f IN )• Transmission Line– Clock Line Longer Than t r / (6 * Delay)Should Be Properly Terminated37The ADC clock signal can add noise to the system if proper care is not taken in its handling.Improper routing of the clock line can cause clock noise to be coupled into the analog signalchain.A clock signal that has cycle-to-cycle variation in its duty cycle is said to exhibit jitter. Clockjitter causes an uncertainty in the precise sampling time, resulting in a reduction of dynamicperformance. Jitter can result from the use of a poor clock source, poor layout and groundingand from energy being coupled into the clock line from other signal sources. Sometimes youwill see this formula as Max Jitter = (V IN_P-P / V FS )/(2 n π f IN ), which allows one LSB of noise.Changing 2 n to 2 (n+1) reduces the allowable noise to ½ LSB and is more conservative.Changing the numerator to “1” gives us the allowable jitter for a full-scale input signal that willnot degrade the signal.The clock line should be treated as a transmission line when its length exceeds the clock risetime/(6 x Delay), where “Delay” is the propagation rate of the signal on the board, and is about150ps/inch (6ps/mm) on a board of FR4 material. Since it is a transmission line, the clock lineshould be properly terminated. Other authors use factors of 4 to 5 in place of the 6 shownhere, but these are marginal values. Using (6 * Delay) is more conservative and allows forvariation in the dielectric constant of the board from one manufacturer to another and forlayout variations.ABCs of ADCs - Rev 3, June 2006Authored by: Nicholas “Nick” Gray37Copyright © 2003, 2004, 2006 National SemiconductorCorporationAll rights reserved
Page 1 and 2: ABCs of ADCsAnalog-to-Digital Conve
Page 3 and 4: What Is an ADC?• Mixed-Signal Dev
Page 5 and 6: Least Significant Bit (LSB)andMost
Page 7 and 8: Quantization Error111Digital Output
Page 9 and 10: Offset Error111OUTPUT CODE110101100
Page 11 and 12: Gain Error (Full-Scale GainError)Ga
Page 13 and 14: DNL1111101010.3 LSB;DNL = -0.7Ideal
Page 15 and 16: Integral Non-Linearity (INL)orInteg
Page 17 and 18: Total Unadjusted Error101OUTPUT COD
Page 19 and 20: THD - Total HarmonicDistortionAnalo
Page 21 and 22: 1Signal-to-Noise and Distortion(SIN
Page 23 and 24: ENOB - Effective Number OfBits• E
Page 25 and 26: Input Dynamic RangeDynamic Range is
Page 27 and 28: Sources of Noiseand DistortionABCs
Page 29 and 30: Inadequate Supply Bypassing• Nois
Page 31 and 32: V A - DR Decoupling• ADC Outputs
Page 33 and 34: Output to Input Coupling• Output
Page 35: Noisy Components/Circuitry• ADC I
Page 39 and 40: Common Design Mistakes• Inadequat
Page 41 and 42: Noisy Components/Circuitry• ADC I
Page 43 and 44: Better Conditioning Circuitry22 220
Page 45 and 46: Resistor Pack Danger500*V REF +V RE
Page 47 and 48: Clock Noise• Clock Can Add Noise
Page 49 and 50: Excessive Clock Jitter (cont’d)No
Page 51 and 52: Treating the Clock LineAs a Trace
Page 53 and 54: A Better Reference CircuitLM4040-4.
Page 55 and 56: High Speed ADCs FromNational: 10-bi
Page 57 and 58: High Speed ADCs FromNational: 14 &
Page 59 and 60: Other General Purpose ADCsFrom Nati
Page 61 and 62: ADC Web Site• Site: www.national.
Page 63 and 64: Absolute Maximum Ratings - Voltages

ABCs of ADCs - Analog-to-Digital Converter Basics (PDF)

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