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ABCs of ADCs - Analog-to-Digital Converter Basics (PDF)

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Watch the Time Constant!• Reduced Amplitude With Increasing DataRate• Difficulty Capturing Data– Shortened Capture Window– May Not Cross Logic Threshold34The time constant <strong>of</strong> the series output resis<strong>to</strong>rs and the capacitances after those resis<strong>to</strong>rs forma time constant that slows the slew rate <strong>of</strong> the output. Also, that time constant reduces theoutput amplitude as the output data rate increases. This can make it difficult <strong>to</strong> capture theoutput data because the capture window is reduced. As the time constant becomes longer orthe output data rate becomes faster we may find that the signal does not even cross the logicthreshold and no data is captured at all.Be careful <strong>of</strong> this time constant. At very high frequencies it may not be practical <strong>to</strong> use seriesresis<strong>to</strong>rs at the ADC output. When this is the case, it is absolutely essential <strong>to</strong> have the drivencircuit very close <strong>to</strong> the ADC output pins and <strong>to</strong> use a data receiving device with a very lowinput capacitance.<strong>ABCs</strong> <strong>of</strong> <strong>ADCs</strong> - Rev 3, June 2006Authored by: Nicholas “Nick” Gray34Copyright © 2003, 2004, 2006 National Semiconduc<strong>to</strong>rCorporationAll rights reserved

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