ABCs of ADCs - Analog-to-Digital Converter Basics (PDF)

Clock Noise• Clock Can Add Noise to Conversion• Clock Can Be Noisy, Exhibiting Jitter– For Ideal SNR,Max Jitter = V IN(P_P) / (V FS x 2 (n+1) x π x f IN )• Transmission Line– Clock Line Longer Than t r / (6 x Delay)Should Be Terminated47The ADC clock signal can add noise and distortion to the system if proper care is not taken inits handling.Improper routing of the clock line can cause clock noise to be coupled into the analog signalchain.A clock signal that has cycle-to-cycle variation in its duty cycle is said to exhibit jitter. Clockjitter causes an uncertainty in the precise sampling time, resulting in a reduction of dynamicperformance. Jitter can result from the use of a poor clock source, poor layout and groundingand from energy being coupled into the clock line from other signal sources.The clock line should be treated as a transmission line when its length exceeds the clock risetime/(6 x Delay), where “Delay” is the propagation rate of the signal on the board, which isabout 150ps/inch (60ps/cm) on a board of FR4 material.ABCs of ADCs - Rev 3, June 2006Authored by: Nicholas “Nick” Gray47Copyright © 2003, 2004, 2006 National SemiconductorCorporationAll rights reserved