March - April 2010 - Chip Scale Review

State-of-the-art and Trends in 3D IntegrationMaking good progress, but major challenges still lie aheadBy John H. Lau [Industrial Technology Research Institute, Taiwan, ROC]3D integration consists of 3D IC and Figure 2) by stacking memory chipspackaging, 3D IC integration, and with wire bonds and die attachments.3D Si integration. They are different Today, 28-chip memory stacking is notand in general the TSV (through-silicon via) uncommon. Package-on-package (PoP),separates 3D IC packaging from 3D IC such as a flip-chip with solder bumpsintegration and 3D Si integration since the attached to a substrate which is supportinglatter two use TSV but 3D IC packaging two stacked chips with wire bonds, isdoes not. TSV for 3D integration is a morethan-26-year-oldtechnology. Even the and PoP are mature technologies in highshown in Figure 2. 3D memory stackingcoplanar GaAs RF MMIC (monolithic volume production (Figure 1 and FigureFigure 3. Moore’s law versus more-than-Mooremicrowave integrated circuit) used via hole 2) 1,2 and will not be discussed.grounding technology in 1975 (35 years(when there are volumes) the packagingago), but it was not for 3D integration. In 3D IC Integration Technology assembly and test houses will do it all.this investigation, TSV (with a new concept As shown in Figure 3, while they are The Holy Grail of 3D IC integrationthat every chip could have two active different, both 3D IC integration and 3D Si (heterogeneous integration) is shown insurfaces) is the focus. State-of-the-art, key integration are more-than-Moore Figure 3, where some of the chips, for example,differences, trends of these three technologies.microdisplay, microelectromechanicaltechnologies, and a 3D integration roadmap FEOL (Front End of Line) is usually systems (MEMS), opto, memory,are presented.performed in semiconductor fabrication microprocessor, optoelectronic, multipleplants (commonly called fabs) to pattern output dc-dc converter, application specific3D IC Packaging Technology active devices such as transistors. The IC (ASIC), microcontroller unit (MCU), digital3D IC packaging consists of two or more process is from a bare wafer to passivation, signal processor (DSP), microbattery, andconventional components (packages) which covers everything except the analog-to-digital (A/D) mixed signal arestacked in the vertical direction. The most bonding pads for the next level of combined and stacked in three dimensions.common is 3D memory stacking (Figure 1 interconnects.Two examples are shown in Figure 2. EightBEOL (Back End of Line) is usually memory chips, each 50μm thick, are stackedperformed in packaging assembly and test with microbumps and TSVs. Thirty two chips,houses and it involves everything after each 20μm thick, are stacked in a chip frompassivation, for example, UBM (under Samsung. Usually the electricalbump metallurgy), wire bonding, performance of 3D IC integration is bettermetallization, wafer bumping, backgrinding, than that of 2D SoC (system-on-chip) asdicing, assembly, and testing right before shown in Figure 3. However, there are majorPCB assembly.challenges in this quest.MEOL (Mid-End of Line) is performed Just as with many other newby combining some of the FEOL and BEOL technologies, 3D IC integration still facesFigure 1. 3D Integration Technologies versus technologies into a 3D IC integration many critical issues 1,2 :Maturity●technology which involves, for example, Known good dice (KGDs) are required.●TSV, microbumps, thin-wafer handling, Design guidelines and software aremetallization, UBM, wafer bumping, not available.●backgrinding, dicing, assembly, and testing. Test methods and equipment areThus, 3D IC integration must be executed lacking.●in the fabs and packaging assembly and TSV with redistribution layers (RDL)test houses. However, since the fabs’ are usually required.●equipment and personnel are too expensive Microbumps are usually required.●for making 3D IC integration and final test Wafer thinning and thin wafer handlingright before the printed circuit board (PCB) during processing are necessary.●assembly (which are not their core High equipment accuracy is necessaryFigure 2. 3D Integration Roadmap competence or major business), eventually for alignments.22 Chip Scale Review. March/April 2010 . [ChipScaleReview.com]