March - April 2010 - Chip Scale Review

More documents

Recommendations

Info

Figure 15. Comparison of tiny vias with 3Dintegration TSVs28Chip Scale Review. March/April 2010 . [ChipScaleReview.com]International Electron Devices Meeting,(IEDM 2006), San Francisco, CA,December 11-13, 2006, pp. 367-370.5. Burns, J., Aull, B., Keast, C., Chen, C.,Chen, C. Keast, C., Knecht, J.,Suntharalingam, V., Warner, K., Wyatt, P.,and Yost, D., “A Wafer-Scale 3-D CircuitIntegration Technology”, IEEETransactions on Electron Devices, Vol. 53,No. 10, October 2006, pp. 2507-2516.6. Sekiguchi, M., Numata, H., Sato, N.,Shirakawa, T., Matsuo, M., Yoshikawa, H.,Yanagida, M., Nakayoshi, H., andTakahashi, K., “Novel Low Cost Integrationof Through Chip Interconnection andApplication to CMOS Image Sensor”, IEEEProceedings of Electronic Componentsand Technology Conference, San Diego,CA, May 2006, pp. 1367-1374.7. Zhang, X., T. Chai, J. H. Lau, C.Selvanayagam, K. Biswas, S. Liu, D.Pinjala, G. Tang, Y. Ong, S. Vempati, E.Wai, H. Li, B. Liao, N. Ranganathan, V.Kripesh, J. Sun, J. Doricko, and C. Vath,“Development of Through Silicon Via(TSV) Interposer Technology for LargeDie (21x21mm) Fine-pitch Cu/low-kFCBGA Package”, IEEE Proceedings ofElectronic, Components & TechnologyConference, San Diego, CA, May, 2009,pp. 305-312. (Also, accepted forpublication in IEEE Transactions inAdvanced Packaging.)8. Selvanayagam, C., J. H. Lau, X. Zhang,S. Seah, K. Vaidyanathan, and T. Chai,“Nonlinear Thermal Stress/StrainAnalysis of Copper Filled TSV (ThroughSilicon Via) and Their Flip-ChipMicrobumps”, IEEE Transactions inAdvanced Packaging, Vol. 32, No. 4, Nov.2009, pp. 720-728.9. Yu, A., J. H. Lau, Ho, S., Kumar, A., Yin,H., Ching, J., Kripesh, V., Pinjala, D., Chen,S., Chan, C., Chao, C., Chiu, C., Huang, M.,and Chen, C., “Three dimensionalinterconnects with high aspect ratio TSVsand fine pitch solder microbumps.” IEEEProceedings of Electronic Componentsand Technology Conference, San Diego,CA, May 2009, pp. 350-354.10. Zhang, X., A. Kumar, Q. X. Zhang, Y.Y. Ong, S. W. Ho, C. H. Khong, V. Kripesh,J. H. Lau, D.-L. Kwong, V. Sundaram, RaoR. Tummula, Georg Meyer-Berg,“Application of Piezoresistive StressSensors in Ultra Thin Device Handlingand Characterization,” Journal of Sensors& Actuators: A. Physical, Vol. 156, Nov.2009, pp. 2-7.11. Yu, A., J. H. Lau, Ho, S., Kumar, A., Wai,Y., Yu, D., Jong, M., Kripesh, V., Pinjala, D.,Kwong, D., “Study of 15-¦Ìm-pitch soldermicrobumps for 3D IC integration.” IEEEProceedings of Electronic Componentsand Technology Conference, San Diego,CA, May 2009, pp. 6 -10.
Next-Gen Advanced Packages Spell Opportunity forBurn-in and Test CommunityBy Françoise von Trapp, Contributing Editor [3D InCites]Iwore a different hat at this year’sBiTS Workshop, held March 7-9,2010, in Mesa AZ. Yup - I set asidethe 3D crown and my trusty keyboardfor a day, put on the burn-in and test hatprovided by Fred Taber, CEO of BITSWorkshop, and stepped in front of thevideo camera to interview keynotespeakers and be the roving reporter onthe exhibition floor. Here’s a synopsisof some of those discussions.Benefits of adaptive testIn his keynote address, Ken Butler,Fellow at Texas Instruments,discussed the concept of adaptive test,comparing it to traditional testapproaches that involve applying afixed sequence to every device in thesame way. “When you move to anadaptive approach, you take intoaccount that processes vary, materialsvary, and likewise test must vary to dothe best possible thing for eachproduct,” said Butler. Rather than justperforming a one-off test to make rapiddecisions, adaptive allows for dataacquisition, movement, and analysis.While adaptive test doesn’t eliminatethe need for burn-in, it optimizes itsuse. In some cases it equals test timereduction, but more importantly itallows you to learn as much as possiblefrom each wafer in terms of processlearning, device debugging, andquality improvement.From a cost perspective, whileadaptive test may cost more as a unit,the benefit of increased yield drivesthe overall cost down. Butleremphasized the importance of lookingat packaging and test processesholistically, rather than at each unitcost, to get the big picture.Unfortunately, despite the obviousbenefits, the industry is slow to adoptadaptive test. Butler says this is partlydue to lack of infrastructure to supportit: better data bases, better datacommunication mechanisms. But thisalso turns into opportunity, he noted,citing several start-ups such as Optimaland Test Advantage that are workingon the EDA tools and software foradaptive test.Butler’s loudest message to themasses was the importance ofcollaboration. Gone are the days wheneveryone benefits by keepinginformation close to the vest. In theadaptive test world, sharing ofinformation is critical to everyone’ssuccess.Test in tray - If you don’t haveone, get oneTom Di Stefano, Centipede Systems,took the podium to talk about one areaof manufacturing where the back-endguys could take some tips from thefront-end guys to reduce cost and timeto test: handling. “Parts are becomingmore complex faster than we candevelop the tools to deal with them,”he remarked.His idea is to create a “lights-outautomation” process, similar to the oneused in wafer fabs, made easy by theexistence of the front opening unifiedpod (FOUP). However, the front-endhas the advantage of standard waferformats; all the varied packageconfigurations pose a challenge to theback-end. According to Di Stefano,this can be solved by reconstitutingpackaged dice into a rectangular arrayand creating a standard carrier thatappears the same to the automationtools. His company’s test-in-traytechnology enables full automationfrom the time the wafer is diced throughfinal assembly, packaging, and test. “Itprovides a vehicle for handling parts,”explained Di Stefano. “You can test apart before stacking and after in thesame type of tray.” This sounded tome like it could be adapted to testingdelicate 3D TSV stacks. “Absolutely,”said Di Stefano. In fact, he saysthey’ve been prototyping test-in-trayfor thin silicon for two years. Whilethis doesn’t solve the test issuesthemselves, it’s his opinion that itshould take care of the handlingportion.It’s ALWAYS about costBrandon Prior, Prismark Partners,focused his market update report on lowcost packaging and small form factorpackages, offering suggestions on howto reduce manufacturing andproduction costs on mostly mainstreampackages. He talked about whatpackages are being used in the industryand why, and what’s driving folks tolower cost solutions.Addressing the slow moving trend inthe industry, he said wire bond stillholds 80-85% of the market in terms ofunits. There’s been a migration awayfrom leadframe packages towards arraybased or substrate based approaches,and beyond that, flip chip packages,Chip Scale Review. March/April 2010 . [ChipScaleReview.com] 29
Page 4 and 5: 2Chip Scale Review. March/April 201
Page 6: VOLUME 14, NUMBER 2FROM THE PUBLISH
Page 9 and 10: Chip Scale Review. March/April 2010
Page 11 and 12: well as for our customers in Asia w
Page 13 and 14: the signature of apartnership witht
Page 15 and 16: IC Assembly and Test Market Poisedf
Page 17 and 18: Honorable MentionCarsem (M) Sdn. Bh
Page 19 and 20: INTERNATIONAL DIRECTORY OF IC PACKA
Page 21 and 22: INTERNATIONAL DIRECTORY OF IC PACKA
Page 23 and 24: EconomicOutlook 2010By Sandra Winkl
Page 25 and 26: ● Fast chips must be mixed with s
Page 27 and 28: expensive “semiconductor” equip
Page 29: integration technology is far in th
Page 33 and 34: High Temperature Stack-chip, Die-at
Page 35 and 36: Figure 6. Specialty fill-in adhesiv
Page 37 and 38: INTERNATIONAL DIRECTORY OF WAFER-BU
Page 39 and 40: WHAT'S NEW!Nanoscale MEMS Made Insi
Page 41 and 42: PRODUCT SHOWCASECALENDARMay 19-21,

March - April 2010 - Chip Scale Review

Create successful ePaper yourself

Delete template?

Save as template?