March - April 2010 - Chip Scale Review

Figure 10. Cross section showing the highaspect ratio (13.3/1) TSVThin Wafer HandlingTo have high performance, low profile,and lightweight products with 3D ICintegration technology, the thickness of thechips/wafers is usually very thin. Making awafer thin is not a big problem. Most of theback-grinding machines can do the job andgrind the wafers to as thin as 5μm. However,handling thin wafers through all thesemiconductor fabrication and packagingassembly processes is difficult. Usually, thethin wafer is temporarily bonded on asupport wafer. Then it goes through all thesemiconductor fabrication processes suchas metallization, passivation and UBM, andthe packaging processes such asbackgrinding and solder bumping. After allthese, removing the thin wafer from thesupport wafer poses another big challenge.Two equipment groups are available forthin-wafer handling today, namely,3M+SUSS and EVG+Brewer Science.Figure 11 shows a very simple and lowcostsupport-wafer method for thin-wafer(50μm) handling. In order to reduce theresidual stress and remain crack-free duringde-bonding, one must reduce the pitch ofthe release holes (1mm in diameter) on theperforated wafer to 2mm and increase thenumber of perforations on the edge of theFigure 11. A low-cost, thin-wafer handlingmethodsupport wafer. These two optimizeddebonding methods allow more chemicalsolution to uniformly penetrate into thebonding adhesive and eventually debondthe wafer successfully 10 .Low-cost, Lead-free SolderMicrobumpsFor 3D IC integration, chips are verythin and thus conventional flip-chipsolder bumps (~100μm) cannot beused. Instead, very tiny bumps (