Marvell PXA27x Processor Family

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PXA27x Processor Family Design Guide 26.3 Signals .................................................................................................................................... 229 26.4 Block Diagram......................................................................................................................... 230 Appendix A. PXA27x DVK Block Diagrams ................................................................... 233 Appendix B. PXA27x Processor Developer’s Kit (DVK) ............................................... 241 Appendix C. PXA27x DVK Bill-of-Materials.................................................................... 243 Appendix D. PXA27x Processor and PXA25x Processor Differences......................... 245 D.1 Introduction ............................................................................................................................. 245 D.2 System Architecture ................................................................................................................ 245 D.3 Clock and Power Manager......................................................................................................245 D.3.1 Clock Manager ............................................................................................................................. 245 D.3.2 Power Manager ............................................................................................................................ 245 D.4 Internal Memory ...................................................................................................................... 246 D.5 DMA Controller........................................................................................................................ 246 D.6 Memory Controller................................................................................................................... 247 D.7 LCD Controller ........................................................................................................................ 248 D.8 SSP Serial Port ....................................................................................................................... 249 D.9 I2C Bus Interface Unit ............................................................................................................. 249 D.10 UARTs..................................................................................................................................... 250 D.11 Fast Infrared Communication Port .......................................................................................... 250 D.12 USB Device Controller ............................................................................................................ 250 D.13 AC ‘97 ..................................................................................................................................... 250 D.14 I2S (Inter IC Sound Controller)................................................................................................ 251 D.15 MultiMediaCard/SD/SDIO Controller....................................................................................... 251 D.16 Baseband/Multimedia Interface...............................................................................................251 D.17 Memory Stick Host Controller ................................................................................................. 251 D.18 Keypad Interface ..................................................................................................................... 252 D.19 Universal Subscriber ID Interface ...........................................................................................252 D.20 Universal Serial Bus Host Controller....................................................................................... 252 D.21 Real-Time Clock (RTC)........................................................................................................... 252 D.22 Operating System Timers ....................................................................................................... 253 D.23 Pulse-Width Modulator Controller ........................................................................................... 253 D.24 General-Purpose I/O Unit........................................................................................................ 254 D.25 Interrupt Controller .................................................................................................................. 254 D.26 Debug/Test.............................................................................................................................. 255 D.27 Software Debug Module.......................................................................................................... 255 D.28 Test Interface .......................................................................................................................... 255 Doc. No. MV-S301207-00 Rev. A Page 12 Copyright © 2009 Marvell April 6, 2009, Released
Appendix E. Companion Components for PXA27x Processor .................................... 257 E.1 Introduction..............................................................................................................................257 E.2 System Architecture.................................................................................................................257 E.3 Clock and Power Manager ......................................................................................................257 E.3.1 Crystals/Oscillators........................................................................................................................257 E.3.2 PMIC Devices................................................................................................................................257 E.4 Internal Memory.......................................................................................................................258 E.5 DMA Controller ........................................................................................................................258 E.6 Memory Controller ...................................................................................................................259 E.7 LCD Controller .........................................................................................................................259 E.8 SSP Serial Port........................................................................................................................259 E.9 I2C Bus Interface Unit..............................................................................................................259 E.10 UARTs .....................................................................................................................................259 E.11 Fast Infrared Communication Port...........................................................................................259 E.12 USB Device (OTG) Controller..................................................................................................259 E.12.1 USB On-The-Go Transceivers ......................................................................................................259 E.13 AC ‘97 ......................................................................................................................................261 E.14 I2S (Inter IC Sound Controller) ................................................................................................261 E.15 MultiMediaCard/SD/SDIO Controller .......................................................................................261 E.16 Intel ® Mobile Scalable Link......................................................................................................261 E.17 Memory Stick Host Controller ..................................................................................................261 E.18 Keypad Interface......................................................................................................................261 E.19 Universal Subscriber ID Interface ............................................................................................261 E.20 Universal Serial Bus Host Controller .......................................................................................261 E.21 Real-Time Clock (RTC) ...........................................................................................................261 E.22 Operating System Timers ........................................................................................................261 E.23 Pulse-Width Modulator Controller............................................................................................261 E.24 General-Purpose I/O Unit ........................................................................................................261 E.25 Interrupt Controller...................................................................................................................261 E.26 JTAG Interface.........................................................................................................................261 Glossary.......................................................................................................... 263 Copyright © 2009 Marvell Doc. No. MV-S301207-00 Rev. A April 6, 2009, Released Page 13
Page 1 and 2: Cover Marvell ® PXA27x Processor F
Page 3 and 4: Table of Contents Section 1. Introd
Page 5 and 6: 5.5.1 Fly-By DMA Transfers ........
Page 7 and 8: 7.5.8 Active Color, 18-bit per pixe
Page 9 and 10: 15.4 Modes of Operation Overview ..
Page 11: 24.2 Signals ......................
Page 15 and 16: List of Figures Figure 1: PXA27x Pr
Page 17 and 18: Figure 83: TAP Controller State Dia
Page 19 and 20: Table 40: FFUART Interface Signals.
Page 21 and 22: Section 1. Introduction to Part I T
Page 23 and 24: 1.3 Package Introduction The PXA27x
Page 25 and 26: Section 2. PCB Design Guidelines Th
Page 27 and 28: Figure 3: Recommended PCB Layer Ass
Page 29 and 30: Figure 5: VF-BGA 13mm x 13mm Compon
Page 31 and 32: Figure 7: PBGA 23mm x 23mm Componen
Page 33 and 34: 2.2.3.2 FS-CSP Escape Routing This
Page 35 and 36: Figure 10: Recommended Mobile Hands
Page 37 and 38: Figure 11: FS-CSP (14x14) Tray Spec
Page 39 and 40: Section 3. Design Check List For de
Page 41 and 42: Section 4. Mixed Voltage Design Con
Page 43 and 44: Figure 13: Minimal Voltage Regulato
Page 45 and 46: Section 5. Power Measurements 5.1 O
Page 47 and 48: • Ensure TDI and TMS pins are pul
Page 49 and 50: Section 1. Introduction to Part II
Page 51 and 52: Section 2. Package and Pins Refer t
Page 53 and 54: Section 3. Clocks and Power Interfa
Page 55 and 56: 3.2.3 Power Enable (PWR_EN) PWR_EN
Page 57 and 58: Figure 14: Typical Battery and Exte
Page 59 and 60: Note The oscillator-output-high-dri
Page 61 and 62: Section 4. Internal SRAM There is n
Page 63 and 64:
Section 5. DMA Controller Interface
Page 65 and 66:
5.5.1.1 Signals See Table 10 for th
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Figure 18: Companion Chip Requestin
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Section 6. System Memory Interface
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Table 13: PXA27x Processor Memory C
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Figure 18: General Memory Interface
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Figure 19: PXA27x Processor Memory
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6.5 Modes of Operation Overview Ref
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Figure 22: SDRAM Memory System Exam
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Table 18: Device 1 x 12 x 8 BS0 A11
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Table 20: Signal Name Flash Interfa
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6.5.3 ROM Interface 6.5.3.1 ROM Sig
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Table 22: Signal Name SRAM Interfac
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6.5.5 Variable Latency Input/Output
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6.5.5.3 VLIO Memory Layout Notes Re
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Refer to Marvell ® PXA270 Processo
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Figure 28: External Logic for a Two
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esponsibility for SDRAM integrity d
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Figure 29: Alternate Bus Master Mod
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Section 7. LCD Interface This chapt
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Table 27: LCD Controller Data Pin U
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7.5 Modes of Operation Overview 7.5
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Table 29: Passive Display Pins Requ
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Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Table 33: LCD Interface Signal List
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7.5.7.1 Signals The signals in Tabl
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7.5.8.1 Signals The signals in Tabl
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7.5.9.1 Signals For active displays
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Section 8. SSP Port Interface 8.1 O
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Table 37: SSP Serial Port I/O Signa
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Figure 41: External Clock Enable Co
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Section 9. Inter-Integrated Circuit
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. Figure 44: Using an Analog Switch
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Section 10.UART Interfaces This cha
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Table 39: UART Signal Descriptions
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10.3.2 Bluetooth UART The BTUART is
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Section 11. Fast Infrared Interface
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Section 12.USB Client Controller Th
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• A more inexpensive solution is
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• During sleep and deep sleep mod
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Figure 54: Host Port 2 OTG Transcei
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• UDC • D+, D-, and transmit en
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Figure 57: Connection to OTG ID USB
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Table 47: Input from External USB T
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Section 13.AC ’97 This chapter de
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5. Enter sleep mode as outlined in
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Section 14.I 2 S Interface This cha
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Figure 60: I 2 S Controller Interfa
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Figure 61: PXA27x Processor Provide
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Section 15.MultiMediaCard/SD/SDIO C
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Table 54: MMC/SD/SDIO Controller Su
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See Figure 64 for the detailed sche
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Figure 65: SD and SDIO Protocol Int
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Table 58: SD/SDIO Card Pull-Up and
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See Figure 66 for illustration of a
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Section 16.Baseband Interface 16.1
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Section 17.Keypad Interface This ch
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17.4 Layout Notes This section has
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Figure 69: Keypad Matrix and Direct
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17.5.3 Keypad Matrix and Direct Key
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Section 18.USIM Controller Interfac
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18.2.2 USIM Card Interface Signals
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Figure 73: Connectivity USIM Card a
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Section 19.Universal Serial Bus Hos
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Figure 75: PXA27x Processor Host 2
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Section 20.Real Time Clock Interfac
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Section 21.OS Timer Interface This
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21.3.4 Output Control This block co
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Section 22.Pulse-Width Modulator In
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Section 23.General Purpose Input/Ou
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causes extraneous resets or interru
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Section 24.Interrupt Interface This
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Figure 80: Interrupt Controller Blo
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Section 25.JTAG Debug This chapter
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Table 69: TAP Controller Pin Defini
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Figure 82: PXA27x Processor Scan Ch
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Table 71: IEEE 1149.1 Boundary-Scan
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25.4.4.3 Data-Specific Registers Da
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25.4.5.3 Select-DR-Scan State The S
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25.4.5.14Pause-IR State The Pause-I
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Section 26.Quick Capture Interface
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Figure 85: Interface Options Summar
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Appendix A. PXA27x DVK Block Diagra
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Figure 87: Main Board Block Diagram
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Figure 89: Liquid Crystal Display B
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Figure 91: Keyboard Block Diagram F
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Appendix B. PXA27x Processor Develo
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Appendix C. PXA27x DVK Bill-of-Mate
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Appendix D. PXA27x Processor and PX
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DSADR16 - DSADR31 DTADR16 - DTADR31
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- FBR1-FBR6 registers added to supp
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• An optional output AC97_SYSCLK
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- The RTSR register has 12 new alar
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Note The only register that remains
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Appendix E. Companion Components fo
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E.6 Memory Controller E.7 LCD Contr
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E.13 AC ‘97 E.14 I 2 S (Inter IC
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Glossary 3G. An industry term used
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Circuit Switched. Used by wireless
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Endpoint Direction. The direction o
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HSTL. High-Speed Transceiver Logic
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inter-symbol interference, because
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SAW. Surface Acoustic Wave filter.
Page 273 and 274:
TPV. Third Party Vendor Transaction
Page 275:
Back Cover Marvell Semiconductor, I
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Marvell PXA27x Processor Family

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