Marvell PXA27x Processor Family

PXA27x Processor Family
Design Guide
5.3 Achieve Minimum Power Usage During All Power
Modes
Methods for achieving the lowest power usage during all power modes:
• Connecting the crystal signals to an external differential oscillator achieves the least amount of power
consumed by the PXA27x processor. Yet, the power consumed by the differential oscillator are considered for
total system power usage. Exercise special care when selecting an external oscillator rather than an external
crystal. Verify that the external oscillator is equally or more efficient than the PXA27x processor using a
crystal.
• Design the system so that all power domains uses the lower voltage level supported within the specifications,
that is, VCC_MEM – 1.8 V.
• Ensure I/O voltage levels track power domain levels, that is, for VCC_MEM – 1.8 V, all MD pins must drive at
1.8 V, otherwise it could cause negative current.
• Ideally, the system design allows measurements of power across all domains individually, helping the
designer in isolating high current problems down to a specific voltage domain.
• Disable all internal pull-ups/pull-downs on GPIO, which is accomplished through PTCR register settings.
• Clearly define clock and memory controller settings.
5.4 Achieve Minimum Power Usage During Deep Sleep
Methods for achieving lowest power usage during deep sleep power modes:
• Ground all non VCC_BATT power domains to enable the designer find the lowest power consumption and
validate the design.
• Monitor and register temperature sensitivity.
• Ensure TDI and TMS pins are pulled high or left floating.
• Ensure the USBC differential inputs (USBCP and USBCN) are pulled high or left floating with no impact to
OTG pins.
• Enable DC-DC internal power supply.
• Ensure DC converter caps are connected properly.
5.5 Achieve Minimum Power Usage During Sleep
Methods used for achieving lowest power usage during sleep power modes:
• Ground SRAM/PLL/Core power domains to enable the designer find the lowest power consumption and
validate the design.
• Configure GPIO signals of the PXA27x processor as input and drive a low from external source.
Programmers can use PGSR/FS (GPIOs in O/P mode).
• Ensure TDI and TMS pins are pulled high or left floating.
• Ensure the USBC differential inputs (USBCP and USBCN) are pulled high or left floating with no impact to
OTG pins.
• Enable DC-DC internal power supply.
5.6 Achieve Minimum Power Usage During Standby
Methods used to achieve lowest power usage during standby power modes:
• Ensure VCC_CORE and VCC_SRAM voltage is at 1.1 V.
• Configure GPIO signals of the PXA27x processor as input and drive a low from external source.
Programmers can use PGSR/FS (GPIOs in O/P mode).
Doc. No. MV-S301207-00 Rev. A
Page 46
Copyright © 2009 Marvell
April 6, 2009, Released