Marvell PXA27x Processor Family

PXA27x Processor Family
Design Guide
5.4 Achieve Minimum Power Usage During Deep Sleep................................................................ 46
5.5 Achieve Minimum Power Usage During Sleep ......................................................................... 46
5.6 Achieve Minimum Power Usage During Standby ..................................................................... 46
5.7 Achieve Minimum Power Usage During Idle/13M/Run/Turbo................................................... 47
Section 1. Introduction to Part II....................................................................................... 49
Section 2. Package and Pins ............................................................................................ 51
Section 3. Clocks and Power Interface ............................................................................ 53
3.1 Overview ................................................................................................................................... 53
3.2 Signals ...................................................................................................................................... 53
3.2.1 Clock Interface Signals................................................................................................................... 53
3.2.2 Power Manager Interface Control Signals...................................................................................... 54
3.2.3 Power Enable (PWR_EN) .............................................................................................................. 55
3.2.3.1 System Power Enable (SYS_EN) ............................................................................................ 55
3.2.3.2 Power Manager I2C Clock (PWR_SCL)................................................................................... 55
3.2.3.3 Power Manager I2C Data (PWR_SDA).................................................................................... 55
3.2.3.4 nVDD_FAULT .......................................................................................................................... 55
3.2.3.5 nBATT_FAULT......................................................................................................................... 55
3.3 Block Diagram........................................................................................................................... 56
3.4 Layout Notes ............................................................................................................................. 57
3.5 Modes of Operations................................................................................................................. 58
3.5.1 Clock Interface................................................................................................................................ 58
3.5.1.1 Using the On-Chip Oscillator with a 32.768-KHz Crystal ......................................................... 58
3.5.1.2 Using an External 32.768-KHz Clock ....................................................................................... 58
3.5.1.3 Using the On-Chip Oscillator with a 13.000-MHz Crystal......................................................... 59
3.5.1.4 Using an External 13.00-MHz Clock ........................................................................................ 59
3.5.2 Power Interface .............................................................................................................................. 59
3.5.2.1 Power Supplies ........................................................................................................................ 60
Section 4. Internal SRAM .................................................................................................. 61
4.1 Overview ................................................................................................................................... 61
4.2 Signals ...................................................................................................................................... 61
4.3 Block Diagram........................................................................................................................... 61
4.4 Layout Notes ............................................................................................................................. 62
Section 5. DMA Controller Interface................................................................................. 63
5.1 Overview ................................................................................................................................... 63
5.2 Signals ...................................................................................................................................... 63
5.3 Block Diagram........................................................................................................................... 63
5.4 Layout Notes ............................................................................................................................. 64
5.5 Modes of Operation................................................................................................................... 64
Doc. No. MV-S301207-00 Rev. A
Page 4
Copyright © 2009 Marvell
April 6, 2009, Released