Marvell PXA27x Processor Family

PXA27x Processor Family
Design Guide
Table 6:
External Power Supply Descriptions
Name Enable Units Default
Voltage
(V)
Allowed Levels
(V)
Tolerance
(%)
VCC_BATT None Sleep-active units, oscillators 3.0 3.0 ±25
VCC_IO SYS_EN Peripheral I/O 3.3 3.0, 3.3 ±10
VCC_LCD SYS_EN LCD I/O 3.3 1.8, 2.5, 3.0, 3.3 ±10
VCC_USB SYS_EN USB I/O 3.3 3.0, 3.3 ±10
VCC_MEM SYS_EN Memory Controller Interface 3.3 1.8, 2.5, 3.0, 3.3 ±10
VCC_BB SYS_EN Baseband Interface 3.3 1.8, 2.5, 3.0, 3.3 ±10
VCC_USIM 1 SYS_EN USIM Interface 3.3 1.8, 3.0, 3.3 ±10
VCC_PLL PWR_EN Phase Locked Loops 1.3 1.3 ±10
VCC_SRAM PWR_EN Internal SRAM units 1.1 1.1 ±10
VCC_CORE PWR_EN All other internal units any 2 variable 0.85-1.55 ±10
NOTE:
1. VCC_USIM must be held to the VCC_IO specification when using alternate function other than USIM signals.
2. Any legal voltage between 0.85 V and 1.55 V is valid. There is no default.
4.2 Example Power Supply Utilizing Minimal Regulators
See Figure 13 for an example of a power supply system for the PXA27x processor that uses the minimum number
of voltage supplies.
The 1.8 V regulators are shown in dashed lines to indicate where the regulators are used. Use either the dashed
black lines or the dashed lines if that peripheral is used in the system. However, ensure both voltages (if used) are
not connected together.
Doc. No. MV-S301207-00 Rev. A
Page 42
Copyright © 2009 Marvell
April 6, 2009, Released