Marvell PXA27x Processor Family

PXA27x Processor Family
Design Guide
List of Tables
Table 1: Related Documentation ................................................................................................................... 21
Table 2: Recommended PCB Design Guidelines .......................................................................................... 25
Table 3: PCB Dimensions for Copper-Defined Land Pads ............................................................................ 32
Table 4: PCB Dimensions for Copper Defined Land Pads ............................................................................ 33
Table 5: PCB Dimensions for Copper-Defined Land Pads ............................................................................ 34
Table 6: External Power Supply Descriptions................................................................................................ 42
Table 7: Clock Interface Signals .................................................................................................................... 53
Table 8: Power Controller Interface Signals .................................................................................................. 54
Table 9: DMA Interface Signals ..................................................................................................................... 63
Table 10: Fly-By DMA Transfer Signals........................................................................................................... 65
Table 11: Flow-Through DMA Transfer Signals............................................................................................... 66
Table 12: Memory Address Map...................................................................................................................... 69
Table 13: PXA27x Processor Memory Controller I/O Signals.......................................................................... 70
Table 14: Minimum and Maximum Trace Lengths for the SDRAM Signals (Excluding SDCLK and
SDCAS) ........................................................................................................................................... 74
Table 15: Minimum and Maximum Trace Lengths for the SDCLK and SDCAS signals ............................ 75
Table 16: SDRAM I/O Signals ......................................................................................................................... 77
Table 17: SDRAM Memory Types Supported by PXA27x Processor.............................................................. 80
Table 18: Normal and Alternate Mode Memory Address Signal Mapping ....................................................... 80
Table 19: SA-1110 Address Compatibility Mode Memory Address Signal Mapping ....................................... 81
Table 20: Flash Interface Signals ................................................................................................................... 83
Table 21: ROM Interface Signals..................................................................................................................... 85
Table 22: SRAM Interface Signals................................................................................................................... 86
Table 23: VLIO Memory Interface Signals ....................................................................................................... 89
Table 24: PC Card Interface Signals ............................................................................................................... 91
Table 25: Alternate Bus Master Interface Signals............................................................................................ 97
Table 26: LCD Interface Signal List ............................................................................................................... 102
Table 27: LCD Controller Data Pin Utilization................................................................................................ 103
Table 28: Passive Display Pins Required ...................................................................................................... 105
Table 29: Passive Display Pins Required ...................................................................................................... 107
Table 30: Passive Display Pins Required ...................................................................................................... 108
Table 31: Passive Display Pins Required ...................................................................................................... 110
Table 32: Passive Display Pins Required ...................................................................................................... 112
Table 33: LCD Interface Signal List ............................................................................................................... 115
Table 34: LCD Interface Signal List ............................................................................................................... 117
Table 35: LCD Interface Signal List ............................................................................................................... 119
Table 36: Active Display Pins Required......................................................................................................... 121
Table 37: SSP Serial Port I/O Signals ........................................................................................................... 123
Table 38: I2C Signal Description ................................................................................................................... 129
Table 39: UART Signal Descriptions ............................................................................................................. 134
Re
Doc. No. MV-S301207-00 Rev. A
Page 18
Copyright © 2009 Marvell
April 6, 2009, Released