Marvell PXA27x Processor Family

PXA27x Processor Family
Design Guide
Figure 39: Standard SSP Configuration Scheme Block Diagram ................................................................... 125
Figure 40: External Clock Source Configuration Scheme Block Diagram....................................................... 126
Figure 41: External Clock Enable Configuration Scheme Block Diagram....................................................... 127
Figure 42: Internal Clock Enable Configuration Scheme Block Diagram........................................................ 128
Figure 43: Linear Technology DAC with I2C Interface.................................................................................... 130
Figure 44: Using an Analog Switch to Allow a Second CF Card..................................................................... 131
Figure 45: I 2 C Pull-Ups and Pull-Downs ......................................................................................................... 132
Figure 46: FFUART Interface Block Diagram.................................................................................................. 136
Figure 47: BTUART Interface Block Diagram ................................................................................................. 137
Figure 48: STUART Interface Block Diagram ................................................................................................. 138
Figure 49: Fast Infrared Controller Port Interface Block Diagram ................................................................... 140
Figure 50: USB Client Interface Block Diagram .............................................................................................. 142
Figure 51: Self Powered Device when GPIOn and GPIOx are Different Pins................................................. 143
Figure 52: Self-Powered Device when GPIOn and GPIOx are Same Pins..................................................... 144
Figure 53: USB OTG Configurations............................................................................................................... 146
Figure 54: Host Port 2 OTG Transceiver ........................................................................................................ 147
Figure 55: Connection to External OTG Transceiver ...................................................................................... 148
Figure 56: Connection to External OTG Charge Pump................................................................................... 150
Figure 57: Connection to OTG ID ................................................................................................................... 151
Figure 58: PXA27x Processor Connection to External USB Transceiver ....................................................... 152
Figure 59: AC ‘97 Controller to CODEC Block Diagram ................................................................................. 156
Figure 60: I2S Controller Interface Block Diagram.......................................................................................... 161
Figure 61: PXA27x Processor Provides BITCLK ............................................................................................ 163
Figure 62: PXA27x Processor Receives BITCLK ........................................................................................... 164
Figure 63: MMC Protocol Interface Block Diagram......................................................................................... 168
Figure 64: MMC Protocol Interface Schematic Diagram................................................................................. 169
Figure 65: SD and SDIO Protocol Interface Block Diagram............................................................................ 171
Figure 66: SD and SDIO Protocol Interface Schematic Diagram.................................................................... 172
Figure 67: SPI Protocol Interface Block Diagram............................................................................................ 174
Figure 68: Keypad Interface Block Diagram ................................................................................................... 180
Figure 69: Keypad Matrix and Direct Keys Block Diagram (with No Rotary Encoder).................................... 183
Figure 70: Keypad Matrix and Direct Keys Block Diagram (with One Rotary Encoder).................................. 184
Figure 71: Keypad Matrix and Direct Keys Block Diagram (with Two Rotary Encoders) ................................ 186
Figure 72: Connectivity USIM Card and PXA27x Processor USIM Interface using UVSx signals.................. 190
Figure 73: Connectivity USIM Card and PXA27x Processor USIM Interface Using nUEN............................. 191
Figure 74: USB Host (Port 1 or Port 2) Differential Connections Block Diagram............................................ 194
Figure 75: PXA27x Processor Host 2 Single-Ended Connection to External Transceiver.............................. 195
Figure 76: PXA27x Processor Host 3 Connection to External USB Transceiver............................................ 196
Figure 77: Example HZ_CLK Block Diagram.................................................................................................. 200
Figure 78: OS Timer Block Diagram ............................................................................................................... 202
Figure 79: PWM Block Diagram For Applications Requiring a Filter............................................................... 206
Figure 80: Interrupt Controller Block Diagram................................................................................................. 213
Figure 81: Test Access Port (TAP) Block Diagram ......................................................................................... 216
Figure 82: PXA27x Processor Scan Chain Arrangement ............................................................................... 219
Doc. No. MV-S301207-00 Rev. A
Page 16
Copyright © 2009 Marvell
April 6, 2009, Released