User's Manual - chipdb.org

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3.2.3 Jump/Branch Instructions.............................................................77
3.2.4 Special Instructions ......................................................................81
3.2.5 Coprocessor Instructions ..............................................................83
3.2.6 System Control Coprocessor (CP0) Instructions..........................86
Chapter 4 Pipeline................................................................................89
4.1 General ........................................................................................90
4.1.1 Pipeline Operations ......................................................................92
4.2 Branch Delay...............................................................................94
4.3 Load Delay ..................................................................................95
4.4 Pipeline Operation......................................................................95
4.5 Interlock and Exception Handling..........................................103
4.6 Pipeline Interlocks and Exceptions.........................................106
4.6.1 Pipeline Interlocks......................................................................106
4.6.2 Instruction TLB Miss (ITM) ......................................................107
4.6.3 Instruction Cache Busy (ICB) ....................................................108
4.6.4 Multicycle Instruction Interlock (MCI)......................................109
4.6.5 Load Interlock (LDI) ..................................................................110
4.6.6 Data Cache Miss (DCM)............................................................111
4.6.7 Data Cache Busy (DCB) ............................................................111
4.6.8 CACHE Operation (COp) ..........................................................112
4.6.9 Coprocessor 0 Bypass Interlock (CP0I) .....................................113
4.7 Pipeline Exceptions...................................................................114
4.7.1 Instruction-Independent Exceptions
(Reset, NMI, and Interrupt)........................................................114
4.7.2 Instruction-Dependent Exceptions .............................................115
4.7.3 Interactions between Interlocks and Exceptions ........................115
4.7.4 Exception and Interlock Priorities..............................................116
4.7.5 WB-Stage Interlock and Exception Priorities ............................117
4.7.6 DC-Stage Interlock and Exception Priorities .............................117
4.7.7 EX-Stage Interlock and Exception Priorities .............................118
4.7.8 RF-Stage Interlock and Exception Priorities..............................118
4.7.9 Bypassing ...................................................................................119
4.8 Code Compatibility ..................................................................119
4.9 Write Buffer..............................................................................120
User’s Manual U10504EJ7V0UM00