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Chapter 1 34 Data/Address Control System Interface Instruction Cache Pipeline Control MasterClock Clock Generator CP0 TLB Figure 1-1 Internal Block Diagram User’s <strong>Manual</strong> U10504EJ7V0UM00 Data Cache Instruction Address Execution Unit
1.4.1 Internal Block Configuration User’s <strong>Manual</strong> U10504EJ7V0UM00 General System Interface allows the processor to access external resources such as memories. It contains a 32-bit multiplexed address/data bus, with per-byte parity, clock signals, interrupt request signals, and various control signals. It is not compatible with the System interface bus used on the VR4400 and VR4200. Clock Generator generates a pipeline clock (PClock) based on an externally input clock (MasterClock). The frequency of the PClock can be selected by setting the frequency ratio between the MasterClock and the PClock. This ratio is set using the DivMode pins on power application. (For setting of the DivMode pins, refer to Table 2-2 Clock/Control Interface Signals.) Table 1-1 indicates the selectable frequency ratio. System interface clock ( SClock) usually has the same frequency as the MasterClock. Table 1-1 Frequency Ratio Between PClock and MasterClock Product Name DivMode Pin Selectable Frequency Ratio (MasterClock : PClock) VR4300 DivMode (1 : 0) *1 *2 1 : 1.5 , 1 : 2, 1 : 3, 1 : 4 VR4305 DivMode (1 : 0) 1 : 1, 1 : 2, 1 : 3 VR4310 DivMode (2 : 0) *3 1 : 2, 1 : 2.5 , 1 : 3, 1 : 4, 1 : 5, 1 : 6 *1. Selectable with the 100 MHz model only (With the 133 MHz model, this setting is reserved.) 2. Selectable with the 133 MHz model only (With the 100 MHz model, this setting is reserved.) 3. Selectable with the 167 MHz model only (With the 133 MHz model, this setting is reserved.) If the RP bit of the Status register is set to 1 during operation, the frequencies of * the PClock and SClock can be reduced to 1/4 of the normal frequency . Because the PLL (Phase-Locked Loop) technique is employed, the skew (phase difference) between the external clock and internal operation clock can be minimized. * 100 MHz model of the VR4300 and the VR4305 only Instruction Cache is direct-mapped, virtually-indexed, and physically-tagged. The capacity is 16 KB. Execution Unit has the hardware resources to execute integer and floating-point instructions. It has a 64-bit register file, 64-bit integer/mantissa datapath, and 12bit exponent datapath. It is provided with a dedicated multiplexer in order to process multiply instruction at a high speed. 35
Page 1 and 2: User’s Manual VR4300 TM , VR4305
Page 3 and 4: NOTES FOR CMOS DEVICES 1 PRECAUTION
Page 5 and 6: Regional Information Some informati
Page 7 and 8: Readers Purpose Organization How to
Page 9 and 10: CONTENTS Chapter 1 General.........
Page 11 and 12: Chapter 5 Memory CONTENTS Managemen
Page 13 and 14: 7.4 Fixed-Point Format ............
Page 15 and 16: Chapter 12 System CONTENTS Interfac
Page 17 and 18: 13.3.5 13.3.6 TAP Controller ......
Page 19 and 20: Appendix C Differences CONTENTS fro
Page 21 and 22: LIST OF FIGURES (2/6) Figure No. Ti
Page 27 and 28: LIST OF TABLES (2/4) Table No. Titl
Page 29 and 30: LIST OF TABLES (4/4) Table No. Titl
Page 31 and 32: General This chapter outlines the R
Page 33: 1.2 Ordering Information 1.3 64-Bit
Page 37 and 38: 1.4.2 CPU Registers The processor p
Page 39 and 40: 1.4.3 CPU Instruction Set Overview
Page 41 and 42: 1.4.4 Data Formats and Addressing G
Page 43 and 44: General The CPU uses byte addressin
Page 45 and 46: Register Name Reg. # Index Random E
Page 47 and 48: 1.4.6 Floating-Point Unit (FPU), CP
Page 49 and 50: 1.5.2 Operating Modes Instruction M
Page 51 and 52: Pin Functions User’s Manual U1050
Page 53 and 54: PIN NAME ColdReset : Cold Reset Div
Page 55 and 56: 2.2.2 Clock/Control Interface Signa
Page 57 and 58: DivMode Internal operating frequenc
Page 59 and 60: CPU Instruction Set Summary This ch
Page 61 and 62: Support of the MIPS ISA 3.2 Instruc
Page 63 and 64: Access-Type Mnemonic ( Value) Low-O
Page 65 and 66: Store Byte Store Halfword Store Wor
Page 67 and 68: Store Conditional Store Conditional
Page 69 and 70: Instruction Format and Description
Page 71 and 72: Add Instruction Format and Descript
Page 73 and 74: Instruction Format and Description
Page 75 and 76: Doubleword Shift Right Arithmetic +
Page 77 and 78: 3.2.3 Jump/Branch Instructions CPU
Page 79 and 80: CPU Instruction Set Summary The fol
Page 81 and 82: 3.2.4 Special Instructions CPU Inst
Page 83 and 84: 3.2.5 Coprocessor Instructions CPU
Page 85 and 86:
Table 3-20 Coprocessor Instructions
Page 87 and 88:
Table 3-21 System Control Coprocess
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Pipeline This chapter describes the
Page 91 and 92:
PCycle User’s Manual U10504EJ7V0U
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Cycle IC RF EX DC WB Table 4-1 Desc
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4.3 Load Delay 4.4 Pipeline Operati
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PClock Phase Cycle F1 F2 F1 F2 F1 F
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PClock Phase Cycle Branch on Equal
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PClock Phase Cycle Load Word Instru
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4.5 Interlock and Exception Handlin
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Table 4-2 Description of Pipeline E
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4.6.2 Instruction TLB Miss (ITM) Pi
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4.6.4 Multicycle Instruction Interl
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4.6.6 Data Cache Miss (DCM) Pipelin
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4.6.9 Coprocessor 0 Bypass Interloc
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4.7.2 Instruction-Dependent Excepti
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4.7.5 WB-Stage Interlock and Except
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4.7.9 Bypassing Pipeline In some ca
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Memory Management System The VR4300
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1. Virtual address (VA) represented
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32-bit Mode Address Translation 39
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5.2.1 Operating Modes User’s Manu
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useg (32-bit mode) User’s Manual
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Address Bit Values 32-bit A(31) = 0
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5.2.4 Virtual Addressing in Kernel
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0x BFFF FFFF FFFF FFFF 0x B800 0001
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32-bit Kernel Mode, Kernel Space 0
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64-bit Kernel Mode, User Space (xku
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Memory Management System 64-bit Ker
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5.3.1 Format of a TLB Entry 127 95
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EntryLo0 32-bit Mode EntryLo1 32-bi
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5.4.2 Random Register (1) Memory Ma
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PageMask Register Memory Management
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5.4.5 Processor Revision Identifier
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mPD30210-167 (V R 4310) 010 ® 1:5
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TagLo TagHi Memory Management Syste
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Yes TLB Mod Exception Address Error
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Exception Processing This chapter d
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Exception/Error Level The Kernel mo
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6.3.1 Context Register (4) 32-bit M
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6.3.4 Compare Register (11) 6.3.5 S
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Exception Processing Figure 6-6 sho
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Operating Modes Exception Processin
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6.3.6 Cause Register (13) Exception
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IP7 Exception Processing The V R 43
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6.3.8 WatchLo (18) and WatchHi (19)
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BadVPN2 Area R Area PTEBase Area Th
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6.3.12 Error Exception Program Coun
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Cold Reset, Soft Reset, and NMI TLB
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6.4.4 Cold Reset Exception Cause Pr
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6.4.6 Non-Maskable Interrupt (NMI)
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6.4.8 TLB Exceptions Exception Proc
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Servicing Exception Processing A TL
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Servicing Exception Processing The
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6.4.12 Coprocessor Unusable Excepti
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6.4.14 Trap Exception Cause Process
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6.4.16 Floating-Point Exception Cau
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6.4.18 Interrupt Exception Cause Pr
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BD bit of Cause Register
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EXL = 0? (SR bit 1) (a) Hardware Ye
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Cold Reset, Soft Reset & NMI Except
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Floating-Point Operations User’s
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Floating-Point Registers (FPR) (FR
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7.2.3 Floating-Point Control Regist
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FS bit C Bit User’s Manual U10504
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RM bits Bit 1 Bit 0 0 0 RN 0 1 RZ 1
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7.3 Floating-Point Formats Floating
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Floating-Point Operations The minim
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7.5 FPU Set Overview Floating-Point
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Instruction Format and Description
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Floating-point Truncate To Single F
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Floating-Point Operations fmt appen
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7.5.5 FPU Branch Instructions Float
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FP #1 Run Run • • • Stall •
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7.6 FPU Pipeline Synchronization Fl
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Floating-Point Exceptions This chap
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Figure 8-1 FCR31 Cause/Enable/Flag
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FPU Internal Result User’s Manual
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User’s Manual U10504EJ7V0UM00 Flo
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If Exception Is Enabled: Floating-P
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8.4 Handling of IEEE754 Exceptions
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Initialization Interface This chapt
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9.2 Reset Signal Description This s
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9.2.3 Soft Reset User’s Manual U1
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MasterClock (input) Reset (input) C
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Initialization Interface 3. Make su
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Clock Interface User’s Manual U10
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10.2 Basic System Clocks MasterCloc
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Cycle 1 2 3 4 MasterClock (input) P
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10.3 System Timing Parameters User
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10.5 Connecting Clocks to a Phase-L
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MasterClock V R 4300 MasterClock Sy
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10.6.2 Connecting to a CMOS Discret
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Clock Interface The transmission ti
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Cache Memory This chapter describes
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11.2 Cache Organization V R 4300 Ca
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11.2.2 Organization of the Data Cac
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11.3 Cache Operations User’s Manu
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Data Load Miss If the missed cache
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11.4 Cache States Cache Line Data C
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11.5.2 Instruction Cache State Tran
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System Interface User’s Manual U1
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12.2 System Interface Description 1
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12.2.2 Interface Buses User’s Man
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12.2.4 Issue Cycles Processor Reque
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12.2.5 Handshake Signals EOK Signal
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12.3.2 Moving from Master to Slave
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System Interface When an external a
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12.4.2 Processor Read Request Syste
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12.4.5 External Write Request 12.4.
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12.5.4 Loads or Stores to Uncached
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System Interface Once the processor
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12.6.3 Processor Write Request Prot
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12.6.4 Flow Control of Processor Re
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12.6.6 External Arbitration Protoco
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Restoring Bus Mastership by PReq Si
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System Interface SCycle 1 2 3 4 5 6
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System Interface Figure 12-22 shows
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12.7 Successive Processing of Reque
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12.7.3 Processor Read Request Follo
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12.8 Discarding and Re-Executing Co
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12.8.3 Discarding and Re-Executing
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System Interface SCycle 1 2 3 4 5 6
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12.9.1 Independent Transfer on SysA
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12.11 System Interface Commands and
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System Interface Tables 12-4 throug
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12.11.5 System Interface Data Ident
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12.12 System Interface Addresses Sy
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JTAG Interface User’s Manual U105
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13.2 Signal Summary The JTAG interf
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13.3.2 Bypass Register Board Input
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13.3.4 Test Access Port (TAP) User
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Shift DR (Boundary Scan) State User
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Interrupts Four types of interrupt
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NMI (Internal Register) SClock 14.2
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4 SysAD(4:0) Interrupt Set Value 20
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14.5.2 Masking of Interrupt Request
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Power Management User’s Manual U1
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15.1.3 Power Off Mode User’s Manu
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CPU Instruction Set Details User’
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Table 16-1 CPU Instruction Operatio
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16.2 Load and Store Instructions Ad
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16.3 Jump and Branch Instructions U
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ADD Format: Description: Operation:
Page 373 and 374:
ADDIU Format: Description: Operatio
Page 375 and 376:
AND Format: Description: Operation:
Page 377 and 378:
BCzF 31 26 25 Format: Description:
Page 379 and 380:
BCzFL 31 26 25 COPz BC BCFL 0 1 0 0
Page 381 and 382:
BCzT 31 26 25 Format: Description:
Page 383 and 384:
Branch On Coprocessor z BCzTL True
Page 385 and 386:
BEQ Format: Description: Operation:
Page 387 and 388:
BGEZ Format: Description: Operation
Page 389 and 390:
BGEZALL Format: BGEZALL rs, offset
Page 391 and 392:
BGTZ Format: Description: Operation
Page 393 and 394:
BLEZ Format: Description: Operation
Page 395 and 396:
BLTZ Format: Description: Operation
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BLTZALL Format: BLTZALL rs, offset
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BNE Format: Description: Operation:
Page 401 and 402:
BREAK 31 26 25 Format: BREAK Descri
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CACHE Cache Operation (continued) C
Page 405 and 406:
Operation: Exceptions: Coprocessor
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COPz 31 26 25 24 COPz CO 0 1 0 0 x
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DADD Format: Description: Operation
Page 411 and 412:
Doubleword Add DADDIU Immediate Uns
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DDIV Format: DDIV rs, rt Descriptio
Page 415 and 416:
DIV Format: DIV rs, rt Description:
Page 417 and 418:
DIVU Format: Description: DIVU rs,
Page 419 and 420:
DMFC0 Format: Description: Operatio
Page 421 and 422:
DMULT Doubleword Multiply Format: D
Page 423 and 424:
DSLL Format: Description: Operation
Page 425 and 426:
DSLL32 Format: Description: Operati
Page 427 and 428:
DSRAV Format: Description: Operatio
Page 429 and 430:
DSRL Format: Description: Operation
Page 431 and 432:
Doubleword Shift Right DSRL32 Logic
Page 433 and 434:
DSUBU Format: Description: Operatio
Page 435 and 436:
J 31 26 25 J 0 0 0 0 1 0 6 Format:
Page 437 and 438:
JALR Format: Description: Operation
Page 439 and 440:
LB Format: Description: Operation:
Page 441 and 442:
LD Format: Description: Operation:
Page 443 and 444:
Operation: Exceptions: TLB miss exc
Page 445 and 446:
LDL Operation: Load Doubleword Left
Page 447 and 448:
LDR Format: LDR rt, offset(base) De
Page 449 and 450:
LDR Exceptions: Load Doubleword Rig
Page 451 and 452:
LHU Format: Description: Operation:
Page 453 and 454:
LL Operation: Exceptions: CPU Instr
Page 455 and 456:
CPU Instruction Set Details Load Li
Page 457 and 458:
LUI Format: Description: Operation:
Page 459 and 460:
LWCz Load Word To Coprocessor z For
Page 461 and 462:
LWL Format: Description: LWL rt, of
Page 463 and 464:
Exceptions: CPU Instruction Set Det
Page 465 and 466:
LWR Operation: Load Word Right (con
Page 467 and 468:
LWU Format: Description: Operation:
Page 469 and 470:
MFC0 Format: Description: Operation
Page 471 and 472:
Opcode Bit Encoding: CPU Instructio
Page 473 and 474:
MFLO Format: MFLO rd Description: O
Page 475 and 476:
MTCz Format: Description: Operation
Page 477 and 478:
MTHI 31 26 25 Format: MTHI rs Descr
Page 479 and 480:
Format: Description: MULT rs, rt Us
Page 481 and 482:
MULTU Format: Description: MULTU rs
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NOR Format: Description: Operation:
Page 485 and 486:
ORI Format: Description: Operation:
Page 487 and 488:
SC Format: Description: SC rt, offs
Page 489 and 490:
SCD Format: Description: Store Cond
Page 491 and 492:
SD Format: Description: Operation:
Page 493 and 494:
SDCz Format: Description: SDCz rt,
Page 495 and 496:
SDL Format: Description: SDL rt, of
Page 497 and 498:
SDL Exceptions: Store Doubleword Le
Page 499 and 500:
SDR Operation: Store Doubleword Rig
Page 501 and 502:
SH Format: Description: Operation:
Page 503 and 504:
SLL Format: Description: Operation:
Page 505 and 506:
SLT Format: Description: Operation:
Page 507 and 508:
SLTIU Format: Description: Operatio
Page 509 and 510:
SRA Format: Description: Operation:
Page 511 and 512:
SRL Format: Description: Operation:
Page 513 and 514:
Format: Description: Operation: Exc
Page 515 and 516:
SW Format: Description: Operation:
Page 517 and 518:
Exceptions: TLB miss exception TLB
Page 519 and 520:
CPU Instruction Set Details SWL Sto
Page 521 and 522:
Format: Description: SWR rt, offset
Page 523 and 524:
SWR Exceptions: CPU Instruction Set
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Format: Description: Operation: Exc
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TEQI Format: Description: Operation
Page 529 and 530:
TGEI Trap If Greater Than Or Equal
Page 531 and 532:
TGEU Format: Description: Operation
Page 533 and 534:
TLBR 31 26 25 24 Format: TLBR Descr
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Format: TLBWR Description: Operatio
Page 537 and 538:
TLTI Format: Description: Operation
Page 539 and 540:
TLTU Format: Description: Operation
Page 541 and 542:
TNEI Format: Description: Operation
Page 543 and 544:
XORI Format: Description: Operation
Page 545 and 546:
20...19 0 1 2 3 5 ... 3 0 1 2 3 0 1
Page 547 and 548:
FPU Instruction Set Details User’
Page 549 and 550:
Operation Table 17-1 Valid FPU Inst
Page 551 and 552:
Floating-Point Loads, Stores, and T
Page 553 and 554:
17.3 Load and Store Instructions Us
Page 555 and 556:
17.4 Floating-Point Computational I
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User’s Manual U10504EJ7V0UM00 FPU
Page 559 and 560:
ABS.fmt Format: Description: Operat
Page 561 and 562:
BC1F 31 26 25 COP1 BC BCF 0 1 0 0 0
Page 563 and 564:
BC1T 31 26 COP1 0 1 0 0 0 1 6 Forma
Page 565 and 566:
C.cond.fmt Format: Description: C.c
Page 567 and 568:
CEIL.L.fmt Format: Description: CEI
Page 569 and 570:
CEIL.W.fmt Format: Description: CEI
Page 571 and 572:
CFC1 Format: Description: Operation
Page 573 and 574:
CVT.D.fmt Format: Description: Oper
Page 575 and 576:
CVT.L.fmt Format: Description: CVT.
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CVT.S.fmt Format: Description: Oper
Page 579 and 580:
CVT.W.fmt Format: Description: CVT.
Page 581 and 582:
DIV.fmt Format: Description: Operat
Page 583 and 584:
DMFC1 Operation: Exceptions: Remark
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DMTC1 Operation: Exceptions: Remark
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FLOOR.L.fmt Operation: Remark Excep
Page 589 and 590:
Operation: Exceptions: Coprocessor
Page 591 and 592:
LDC1 Operation: Exceptions: Load Do
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LWC1 Operation: Exceptions: Load Wo
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MOV.fmt Format: Description: Operat
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MUL.fmt Format: Description: Operat
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ROUND.L.fmt Format: Description: RO
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ROUND.W.fmt Format: Description: RO
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SDC1 Format: Description: Store Dou
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SQRT.fmt Format: Description: Opera
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SWC1 Format: Description: SWC1 ft,
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TRUNC.L.fmt Format: Description: TR
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TRUNC.W.fmt Format: Description: TR
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17.6 FPU Instruction Opcode Bit Enc
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PLL Passive Elements User’s Manua
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User’s Manual U10504EJ7V0UM00 PLL
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Coprocessor 0 Hazards User’s Manu
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User’s Manual U10504EJ7V0UM00 Cop
Page 623 and 624:
Page 625 and 626:
Page 627 and 628:
Differences Between the VR4300, VR4
Page 629 and 630:
Differences from VR4400 The VR4300
Page 631 and 632:
B.1.4 Config Register User’s Manu
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B.2 Differences in System Design Us
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Table B-2 Differences in System Des
Page 637 and 638:
B.3.3 Floating-Point Unit Floating-
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Table B-3 Other Differences * 100 M
Page 641 and 642:
Differences from VR4200 The VR4300
Page 643 and 644:
C.1.4 Cache Parity Error Exception
Page 645 and 646:
C.2.3 Package Function System inter
Page 647 and 648:
Restrictions of VR4300 User’s Man
Page 649 and 650:
Index User’s Manual U10504EJ7V0UM
Page 651 and 652:
Defining Access Types ... 62 Discar
Page 653 and 654:
Processor read request ... 301, 306
Page 655:
Facsimile Message From: Name Compan
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