User's Manual - chipdb.org

Chapter 1
36
Coprocessor 0 (CP0) has the memory management unit (MMU) and handles
exception processing. The MMU handles address translation and checks memory
accesses that occur between different memory segments (user, supervisor, or
kernel). The translation lookaside buffer (TLB) is used to translate virtual to
physical addresses.
Data Cache is a direct-mapped, virtually-indexed and physically-tagged writeback
cache. The capacity is 8 KB.
Instruction Address calculates the effective address of the next instruction to be
fetched. It contains the incrementer for the Program Counter (PC), the target
address adder, and the conditional branch address selector.
Pipeline Control ensures the instruction pipeline operates properly (should one
of the following conditions occur: pipeline stall or exception).
User’s Manual U10504EJ7V0UM00