User's Manual - chipdb.org

Chapter 1
1.5 Memory Management System (MMU)
The VR4300 processor has a 32-bit physical addressing range of 4 GB. However,
since it is rare for systems to implement a physical memory space this large, the
CPU provides a logical expansion of memory space to the programmer by
translating addresses into the large virtual address space. The VR4300 processor
supports the following two addressing modes:
• 32-bit mode, in which the virtual address space is divided into 2 GB
per user process and 2 GB for the kernel.
• 64-bit mode, in which the virtual address is expanded to
1 TB (240 bytes) of user virtual address space.
A detailed description of these address spaces is given in Chapter 5 Memory
Management System.
1.5.1 Translation Lookaside Buffer (TLB)
Virtual memory mapping is assisted by a translation lookaside buffer, which holds
virtual-to-physical address translations. This fully-associative, on-chip TLB
contains 32 entries, each of which maps a pair of variable-sized pages of either 4
KB or 16 MB.
Joint TLB (JTLB)
The TLB can hold both instruction and data addresses, and is thus also referred to
as a joint TLB (JTLB).
An address translation value is tagged with the high-order bits of its virtual
address (the number of these bits depends upon the size of the page) and a perprocess
identifier. If there is no matching entry in the TLB, an exception occurs
and software writes the entry contents to the on-chip TLB from a page table in
memory. The JTLB entry to be rewritten is selected by a value in either the
Random or Index register.
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