User's Manual - chipdb.org

16
12.7.1 Successive Processor Write Requests ........................................321
12.7.2 Processor Write Request Followed by Processor
Read Request..............................................................................322
12.7.3 Processor Read Request Followed by Processor
Write Request .............................................................................323
12.7.4 Processor Write Request Followed by External
Write Request .............................................................................324
12.8 Discarding and Re-Executing Commands .............................325
12.8.1 Re-Execution of Processor Commands......................................325
12.8.2 Discarding and Re-Executing Write Command.........................325
12.8.3 Discarding and Re-Executing Read Command..........................327
12.8.4 Executing and Discarding Command.........................................328
12.9 Data Flow Control ....................................................................330
12.9.1 Independent Transfer on SysAD(31:0) Bus ...............................331
12.9.2 System Endianness .....................................................................331
12.10 System Interface Cycle Time...................................................332
12.10.1 Release Latency Time ................................................................332
12.11 System Interface Commands and Data Identifiers ...............333
12.11.1 Command and Data Identifier Syntax ........................................333
12.11.2 System Interface Command Syntax ...........................................334
12.11.3 Read Requests ............................................................................334
12.11.4 Write Requests............................................................................336
12.11.5 System Interface Data Identifier Syntax.....................................337
12.11.6 Data Identifier Bit Definitions....................................................337
12.12 System Interface Addresses.....................................................339
12.12.1 Addressing Conventions.............................................................339
12.12.2 Sequential and Subblock Ordering.............................................339
Chapter 13 JTAG Interface..............................................................341
13.1 Principles of Boundary Scanning............................................342
13.2 Signal Summary........................................................................343
13.3 JTAG Controller and Registers ..............................................344
13.3.1 Instruction Register ....................................................................344
13.3.2 Bypass Register ..........................................................................345
13.3.3 Boundary-Scan Register.............................................................346
13.3.4 Test Access Port (TAP)..............................................................347
User’s Manual U10504EJ7V0UM00