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Conventions Related documents 8 To learn about the overall functions of the VR4300, ® Read this manual in sequential order. To learn about electrical specifications of the VR4300, ® Refer to the data sheet which is separately available. Data significance: Higher digits on the left and lower digits on the right Active low representation: ´´´ (overscore over pin or signal name) *: Footnote for item marked with * in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical binary or decimal ... ´´´´ representation: hexadecimal ...........0´ ´´´´ Prefixes indicating power of 2 (address space, memory capacity): K (kilo) 10 2 = 1024 20 2 M (mega) 2 = 1024 G (giga) 30 3 2 = 1024 T (tera) 40 4 2 = 1024 P (peta) 50 5 2 = 1024 E (exa) 60 6 2 = 1024 See also the following documents. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Document Name Document Number VR4300, VR4305, VR4310 User’s Manual This manual mPD30200, 30210 Data Sheet U10116E VR Series Application Note - Programming Guide U10710E VR4000 Series Application Note - Simulation Guide U11788J (Japanese only) User’s Manual U10504EJ7V0UM00
CONTENTS Chapter 1 General................................................................................31 1.1 Characteristics............................................................................32 1.2 Ordering Information................................................................33 1.3 64-Bit Architecture.....................................................................33 1.4 VR4300 Processor .......................................................................33 1.4.1 Internal Block Configuration .......................................................35 1.4.2 CPU Registers ..............................................................................37 1.4.3 CPU Instruction Set Overview.....................................................39 1.4.4 Data Formats and Addressing ......................................................41 1.4.5 System Control Coprocessor (CP0) .............................................44 1.4.6 Floating-Point Unit (FPU), CP1...................................................47 1.4.7 Internal Cache ..............................................................................47 1.5 Memory Management System (MMU) ....................................48 1.5.1 Translation Lookaside Buffer (TLB) ...........................................48 1.5.2 Operating Modes..........................................................................49 1.6 Instruction Pipeline....................................................................49 Chapter 2 Pin Functions....................................................................51 2.1 Pin Configuration (Top View) ...................................................52 2.2 Pin Functions ..............................................................................54 2.2.1 System Interface Signals ..............................................................54 2.2.2 Clock/Control Interface Signals...................................................55 2.2.3 Interrupt Interface Signals............................................................57 2.2.4 Joint Test Action Group (JTAG) Interface Signals......................58 2.2.5 Initialization Interface Signals .....................................................58 Chapter 3 CPU Instruction Set Summary .................................59 3.1 CPU Instruction Formats ..........................................................60 3.2 Instruction Classes .....................................................................61 3.2.1 Load/Store Instructions ................................................................61 3.2.2 Computational Instructions ..........................................................68 User’s Manual U10504EJ7V0UM00 9
Page 1 and 2: User’s Manual VR4300 TM , VR4305
Page 3 and 4: NOTES FOR CMOS DEVICES 1 PRECAUTION
Page 5 and 6: Regional Information Some informati
Page 7: Readers Purpose Organization How to
Page 11 and 12: Chapter 5 Memory CONTENTS Managemen
Page 13 and 14: 7.4 Fixed-Point Format ............
Page 15 and 16: Chapter 12 System CONTENTS Interfac
Page 17 and 18: 13.3.5 13.3.6 TAP Controller ......
Page 19 and 20: Appendix C Differences CONTENTS fro
Page 21 and 22: LIST OF FIGURES (2/6) Figure No. Ti
Page 27 and 28: LIST OF TABLES (2/4) Table No. Titl
Page 29 and 30: LIST OF TABLES (4/4) Table No. Titl
Page 31 and 32: General This chapter outlines the R
Page 33 and 34: 1.2 Ordering Information 1.3 64-Bit
Page 35 and 36: 1.4.1 Internal Block Configuration
Page 37 and 38: 1.4.2 CPU Registers The processor p
Page 39 and 40: 1.4.3 CPU Instruction Set Overview
Page 41 and 42: 1.4.4 Data Formats and Addressing G
Page 43 and 44: General The CPU uses byte addressin
Page 45 and 46: Register Name Reg. # Index Random E
Page 47 and 48: 1.4.6 Floating-Point Unit (FPU), CP
Page 49 and 50: 1.5.2 Operating Modes Instruction M
Page 51 and 52: Pin Functions User’s Manual U1050
Page 53 and 54: PIN NAME ColdReset : Cold Reset Div
Page 55 and 56: 2.2.2 Clock/Control Interface Signa
Page 57 and 58: DivMode Internal operating frequenc
Page 59 and 60:
CPU Instruction Set Summary This ch
Page 61 and 62:
Support of the MIPS ISA 3.2 Instruc
Page 63 and 64:
Access-Type Mnemonic ( Value) Low-O
Page 65 and 66:
Store Byte Store Halfword Store Wor
Page 67 and 68:
Store Conditional Store Conditional
Page 69 and 70:
Instruction Format and Description
Page 71 and 72:
Add Instruction Format and Descript
Page 73 and 74:
Page 75 and 76:
Doubleword Shift Right Arithmetic +
Page 77 and 78:
3.2.3 Jump/Branch Instructions CPU
Page 79 and 80:
CPU Instruction Set Summary The fol
Page 81 and 82:
3.2.4 Special Instructions CPU Inst
Page 83 and 84:
3.2.5 Coprocessor Instructions CPU
Page 85 and 86:
Table 3-20 Coprocessor Instructions
Page 87 and 88:
Table 3-21 System Control Coprocess
Page 89 and 90:
Pipeline This chapter describes the
Page 91 and 92:
PCycle User’s Manual U10504EJ7V0U
Page 93 and 94:
Cycle IC RF EX DC WB Table 4-1 Desc
Page 95 and 96:
4.3 Load Delay 4.4 Pipeline Operati
Page 97 and 98:
PClock Phase Cycle F1 F2 F1 F2 F1 F
Page 99 and 100:
PClock Phase Cycle Branch on Equal
Page 101 and 102:
PClock Phase Cycle Load Word Instru
Page 103 and 104:
4.5 Interlock and Exception Handlin
Page 105 and 106:
Table 4-2 Description of Pipeline E
Page 107 and 108:
4.6.2 Instruction TLB Miss (ITM) Pi
Page 109 and 110:
4.6.4 Multicycle Instruction Interl
Page 111 and 112:
4.6.6 Data Cache Miss (DCM) Pipelin
Page 113 and 114:
4.6.9 Coprocessor 0 Bypass Interloc
Page 115 and 116:
4.7.2 Instruction-Dependent Excepti
Page 117 and 118:
4.7.5 WB-Stage Interlock and Except
Page 119 and 120:
4.7.9 Bypassing Pipeline In some ca
Page 121 and 122:
Memory Management System The VR4300
Page 123 and 124:
1. Virtual address (VA) represented
Page 125 and 126:
32-bit Mode Address Translation 39
Page 127 and 128:
5.2.1 Operating Modes User’s Manu
Page 129 and 130:
useg (32-bit mode) User’s Manual
Page 131 and 132:
Address Bit Values 32-bit A(31) = 0
Page 133 and 134:
5.2.4 Virtual Addressing in Kernel
Page 135 and 136:
0x BFFF FFFF FFFF FFFF 0x B800 0001
Page 137 and 138:
32-bit Kernel Mode, Kernel Space 0
Page 139 and 140:
64-bit Kernel Mode, User Space (xku
Page 141 and 142:
Memory Management System 64-bit Ker
Page 143 and 144:
5.3.1 Format of a TLB Entry 127 95
Page 145 and 146:
EntryLo0 32-bit Mode EntryLo1 32-bi
Page 147 and 148:
5.4.2 Random Register (1) Memory Ma
Page 149 and 150:
PageMask Register Memory Management
Page 151 and 152:
5.4.5 Processor Revision Identifier
Page 153 and 154:
mPD30210-167 (V R 4310) 010 ® 1:5
Page 155 and 156:
TagLo TagHi Memory Management Syste
Page 157 and 158:
Yes TLB Mod Exception Address Error
Page 159 and 160:
Exception Processing This chapter d
Page 161 and 162:
Exception/Error Level The Kernel mo
Page 163 and 164:
6.3.1 Context Register (4) 32-bit M
Page 165 and 166:
6.3.4 Compare Register (11) 6.3.5 S
Page 167 and 168:
Exception Processing Figure 6-6 sho
Page 169 and 170:
Operating Modes Exception Processin
Page 171 and 172:
6.3.6 Cause Register (13) Exception
Page 173 and 174:
IP7 Exception Processing The V R 43
Page 175 and 176:
6.3.8 WatchLo (18) and WatchHi (19)
Page 177 and 178:
BadVPN2 Area R Area PTEBase Area Th
Page 179 and 180:
6.3.12 Error Exception Program Coun
Page 181 and 182:
Cold Reset, Soft Reset, and NMI TLB
Page 183 and 184:
6.4.4 Cold Reset Exception Cause Pr
Page 185 and 186:
6.4.6 Non-Maskable Interrupt (NMI)
Page 187 and 188:
6.4.8 TLB Exceptions Exception Proc
Page 189 and 190:
Servicing Exception Processing A TL
Page 191 and 192:
Servicing Exception Processing The
Page 193 and 194:
6.4.12 Coprocessor Unusable Excepti
Page 195 and 196:
6.4.14 Trap Exception Cause Process
Page 197 and 198:
6.4.16 Floating-Point Exception Cau
Page 199 and 200:
6.4.18 Interrupt Exception Cause Pr
Page 201 and 202:
BD bit of Cause Register
Page 203 and 204:
EXL = 0? (SR bit 1) (a) Hardware Ye
Page 205 and 206:
Cold Reset, Soft Reset & NMI Except
Page 207 and 208:
Floating-Point Operations User’s
Page 209 and 210:
Floating-Point Registers (FPR) (FR
Page 211 and 212:
7.2.3 Floating-Point Control Regist
Page 213 and 214:
FS bit C Bit User’s Manual U10504
Page 215 and 216:
RM bits Bit 1 Bit 0 0 0 RN 0 1 RZ 1
Page 217 and 218:
7.3 Floating-Point Formats Floating
Page 219 and 220:
Floating-Point Operations The minim
Page 221 and 222:
7.5 FPU Set Overview Floating-Point
Page 223 and 224:
Page 225 and 226:
Floating-point Truncate To Single F
Page 227 and 228:
Floating-Point Operations fmt appen
Page 229 and 230:
7.5.5 FPU Branch Instructions Float
Page 231 and 232:
FP #1 Run Run • • • Stall •
Page 233 and 234:
7.6 FPU Pipeline Synchronization Fl
Page 235 and 236:
Floating-Point Exceptions This chap
Page 237 and 238:
Figure 8-1 FCR31 Cause/Enable/Flag
Page 239 and 240:
FPU Internal Result User’s Manual
Page 241 and 242:
User’s Manual U10504EJ7V0UM00 Flo
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If Exception Is Enabled: Floating-P
Page 245 and 246:
8.4 Handling of IEEE754 Exceptions
Page 247 and 248:
Initialization Interface This chapt
Page 249 and 250:
9.2 Reset Signal Description This s
Page 251 and 252:
9.2.3 Soft Reset User’s Manual U1
Page 253 and 254:
MasterClock (input) Reset (input) C
Page 255 and 256:
Initialization Interface 3. Make su
Page 257 and 258:
Clock Interface User’s Manual U10
Page 259 and 260:
10.2 Basic System Clocks MasterCloc
Page 261 and 262:
Cycle 1 2 3 4 MasterClock (input) P
Page 263 and 264:
10.3 System Timing Parameters User
Page 265 and 266:
10.5 Connecting Clocks to a Phase-L
Page 267 and 268:
MasterClock V R 4300 MasterClock Sy
Page 269 and 270:
10.6.2 Connecting to a CMOS Discret
Page 271 and 272:
Clock Interface The transmission ti
Page 273 and 274:
Cache Memory This chapter describes
Page 275 and 276:
11.2 Cache Organization V R 4300 Ca
Page 277 and 278:
11.2.2 Organization of the Data Cac
Page 279 and 280:
11.3 Cache Operations User’s Manu
Page 281 and 282:
Data Load Miss If the missed cache
Page 283 and 284:
11.4 Cache States Cache Line Data C
Page 285 and 286:
11.5.2 Instruction Cache State Tran
Page 287 and 288:
System Interface User’s Manual U1
Page 289 and 290:
12.2 System Interface Description 1
Page 291 and 292:
12.2.2 Interface Buses User’s Man
Page 293 and 294:
12.2.4 Issue Cycles Processor Reque
Page 295 and 296:
12.2.5 Handshake Signals EOK Signal
Page 297 and 298:
12.3.2 Moving from Master to Slave
Page 299 and 300:
System Interface When an external a
Page 301 and 302:
12.4.2 Processor Read Request Syste
Page 303 and 304:
12.4.5 External Write Request 12.4.
Page 305 and 306:
12.5.4 Loads or Stores to Uncached
Page 307 and 308:
System Interface Once the processor
Page 309 and 310:
12.6.3 Processor Write Request Prot
Page 311 and 312:
12.6.4 Flow Control of Processor Re
Page 313 and 314:
12.6.6 External Arbitration Protoco
Page 315 and 316:
Restoring Bus Mastership by PReq Si
Page 317 and 318:
System Interface SCycle 1 2 3 4 5 6
Page 319 and 320:
System Interface Figure 12-22 shows
Page 321 and 322:
12.7 Successive Processing of Reque
Page 323 and 324:
12.7.3 Processor Read Request Follo
Page 325 and 326:
12.8 Discarding and Re-Executing Co
Page 327 and 328:
12.8.3 Discarding and Re-Executing
Page 329 and 330:
System Interface SCycle 1 2 3 4 5 6
Page 331 and 332:
12.9.1 Independent Transfer on SysA
Page 333 and 334:
12.11 System Interface Commands and
Page 335 and 336:
System Interface Tables 12-4 throug
Page 337 and 338:
12.11.5 System Interface Data Ident
Page 339 and 340:
12.12 System Interface Addresses Sy
Page 341 and 342:
JTAG Interface User’s Manual U105
Page 343 and 344:
13.2 Signal Summary The JTAG interf
Page 345 and 346:
13.3.2 Bypass Register Board Input
Page 347 and 348:
13.3.4 Test Access Port (TAP) User
Page 349 and 350:
Shift DR (Boundary Scan) State User
Page 351 and 352:
Interrupts Four types of interrupt
Page 353 and 354:
NMI (Internal Register) SClock 14.2
Page 355 and 356:
4 SysAD(4:0) Interrupt Set Value 20
Page 357 and 358:
14.5.2 Masking of Interrupt Request
Page 359 and 360:
Power Management User’s Manual U1
Page 361 and 362:
15.1.3 Power Off Mode User’s Manu
Page 363 and 364:
CPU Instruction Set Details User’
Page 365 and 366:
Table 16-1 CPU Instruction Operatio
Page 367 and 368:
16.2 Load and Store Instructions Ad
Page 369 and 370:
16.3 Jump and Branch Instructions U
Page 371 and 372:
ADD Format: Description: Operation:
Page 373 and 374:
ADDIU Format: Description: Operatio
Page 375 and 376:
AND Format: Description: Operation:
Page 377 and 378:
BCzF 31 26 25 Format: Description:
Page 379 and 380:
BCzFL 31 26 25 COPz BC BCFL 0 1 0 0
Page 381 and 382:
BCzT 31 26 25 Format: Description:
Page 383 and 384:
Branch On Coprocessor z BCzTL True
Page 385 and 386:
BEQ Format: Description: Operation:
Page 387 and 388:
BGEZ Format: Description: Operation
Page 389 and 390:
BGEZALL Format: BGEZALL rs, offset
Page 391 and 392:
BGTZ Format: Description: Operation
Page 393 and 394:
BLEZ Format: Description: Operation
Page 395 and 396:
BLTZ Format: Description: Operation
Page 397 and 398:
BLTZALL Format: BLTZALL rs, offset
Page 399 and 400:
BNE Format: Description: Operation:
Page 401 and 402:
BREAK 31 26 25 Format: BREAK Descri
Page 403 and 404:
CACHE Cache Operation (continued) C
Page 405 and 406:
Operation: Exceptions: Coprocessor
Page 407 and 408:
COPz 31 26 25 24 COPz CO 0 1 0 0 x
Page 409 and 410:
DADD Format: Description: Operation
Page 411 and 412:
Doubleword Add DADDIU Immediate Uns
Page 413 and 414:
DDIV Format: DDIV rs, rt Descriptio
Page 415 and 416:
DIV Format: DIV rs, rt Description:
Page 417 and 418:
DIVU Format: Description: DIVU rs,
Page 419 and 420:
DMFC0 Format: Description: Operatio
Page 421 and 422:
DMULT Doubleword Multiply Format: D
Page 423 and 424:
DSLL Format: Description: Operation
Page 425 and 426:
DSLL32 Format: Description: Operati
Page 427 and 428:
DSRAV Format: Description: Operatio
Page 429 and 430:
DSRL Format: Description: Operation
Page 431 and 432:
Doubleword Shift Right DSRL32 Logic
Page 433 and 434:
DSUBU Format: Description: Operatio
Page 435 and 436:
J 31 26 25 J 0 0 0 0 1 0 6 Format:
Page 437 and 438:
JALR Format: Description: Operation
Page 439 and 440:
LB Format: Description: Operation:
Page 441 and 442:
LD Format: Description: Operation:
Page 443 and 444:
Operation: Exceptions: TLB miss exc
Page 445 and 446:
LDL Operation: Load Doubleword Left
Page 447 and 448:
LDR Format: LDR rt, offset(base) De
Page 449 and 450:
LDR Exceptions: Load Doubleword Rig
Page 451 and 452:
LHU Format: Description: Operation:
Page 453 and 454:
LL Operation: Exceptions: CPU Instr
Page 455 and 456:
CPU Instruction Set Details Load Li
Page 457 and 458:
LUI Format: Description: Operation:
Page 459 and 460:
LWCz Load Word To Coprocessor z For
Page 461 and 462:
LWL Format: Description: LWL rt, of
Page 463 and 464:
Exceptions: CPU Instruction Set Det
Page 465 and 466:
LWR Operation: Load Word Right (con
Page 467 and 468:
LWU Format: Description: Operation:
Page 469 and 470:
MFC0 Format: Description: Operation
Page 471 and 472:
Opcode Bit Encoding: CPU Instructio
Page 473 and 474:
MFLO Format: MFLO rd Description: O
Page 475 and 476:
MTCz Format: Description: Operation
Page 477 and 478:
MTHI 31 26 25 Format: MTHI rs Descr
Page 479 and 480:
Format: Description: MULT rs, rt Us
Page 481 and 482:
MULTU Format: Description: MULTU rs
Page 483 and 484:
NOR Format: Description: Operation:
Page 485 and 486:
ORI Format: Description: Operation:
Page 487 and 488:
SC Format: Description: SC rt, offs
Page 489 and 490:
SCD Format: Description: Store Cond
Page 491 and 492:
SD Format: Description: Operation:
Page 493 and 494:
SDCz Format: Description: SDCz rt,
Page 495 and 496:
SDL Format: Description: SDL rt, of
Page 497 and 498:
SDL Exceptions: Store Doubleword Le
Page 499 and 500:
SDR Operation: Store Doubleword Rig
Page 501 and 502:
SH Format: Description: Operation:
Page 503 and 504:
SLL Format: Description: Operation:
Page 505 and 506:
SLT Format: Description: Operation:
Page 507 and 508:
SLTIU Format: Description: Operatio
Page 509 and 510:
SRA Format: Description: Operation:
Page 511 and 512:
SRL Format: Description: Operation:
Page 513 and 514:
Format: Description: Operation: Exc
Page 515 and 516:
SW Format: Description: Operation:
Page 517 and 518:
Exceptions: TLB miss exception TLB
Page 519 and 520:
CPU Instruction Set Details SWL Sto
Page 521 and 522:
Format: Description: SWR rt, offset
Page 523 and 524:
SWR Exceptions: CPU Instruction Set
Page 525 and 526:
Format: Description: Operation: Exc
Page 527 and 528:
TEQI Format: Description: Operation
Page 529 and 530:
TGEI Trap If Greater Than Or Equal
Page 531 and 532:
TGEU Format: Description: Operation
Page 533 and 534:
TLBR 31 26 25 24 Format: TLBR Descr
Page 535 and 536:
Format: TLBWR Description: Operatio
Page 537 and 538:
TLTI Format: Description: Operation
Page 539 and 540:
TLTU Format: Description: Operation
Page 541 and 542:
TNEI Format: Description: Operation
Page 543 and 544:
XORI Format: Description: Operation
Page 545 and 546:
20...19 0 1 2 3 5 ... 3 0 1 2 3 0 1
Page 547 and 548:
FPU Instruction Set Details User’
Page 549 and 550:
Operation Table 17-1 Valid FPU Inst
Page 551 and 552:
Floating-Point Loads, Stores, and T
Page 553 and 554:
17.3 Load and Store Instructions Us
Page 555 and 556:
17.4 Floating-Point Computational I
Page 557 and 558:
User’s Manual U10504EJ7V0UM00 FPU
Page 559 and 560:
ABS.fmt Format: Description: Operat
Page 561 and 562:
BC1F 31 26 25 COP1 BC BCF 0 1 0 0 0
Page 563 and 564:
BC1T 31 26 COP1 0 1 0 0 0 1 6 Forma
Page 565 and 566:
C.cond.fmt Format: Description: C.c
Page 567 and 568:
CEIL.L.fmt Format: Description: CEI
Page 569 and 570:
CEIL.W.fmt Format: Description: CEI
Page 571 and 572:
CFC1 Format: Description: Operation
Page 573 and 574:
CVT.D.fmt Format: Description: Oper
Page 575 and 576:
CVT.L.fmt Format: Description: CVT.
Page 577 and 578:
CVT.S.fmt Format: Description: Oper
Page 579 and 580:
CVT.W.fmt Format: Description: CVT.
Page 581 and 582:
DIV.fmt Format: Description: Operat
Page 583 and 584:
DMFC1 Operation: Exceptions: Remark
Page 585 and 586:
DMTC1 Operation: Exceptions: Remark
Page 587 and 588:
FLOOR.L.fmt Operation: Remark Excep
Page 589 and 590:
Operation: Exceptions: Coprocessor
Page 591 and 592:
LDC1 Operation: Exceptions: Load Do
Page 593 and 594:
LWC1 Operation: Exceptions: Load Wo
Page 595 and 596:
MOV.fmt Format: Description: Operat
Page 597 and 598:
MUL.fmt Format: Description: Operat
Page 599 and 600:
ROUND.L.fmt Format: Description: RO
Page 601 and 602:
ROUND.W.fmt Format: Description: RO
Page 603 and 604:
SDC1 Format: Description: Store Dou
Page 605 and 606:
SQRT.fmt Format: Description: Opera
Page 607 and 608:
SWC1 Format: Description: SWC1 ft,
Page 609 and 610:
TRUNC.L.fmt Format: Description: TR
Page 611 and 612:
TRUNC.W.fmt Format: Description: TR
Page 613 and 614:
17.6 FPU Instruction Opcode Bit Enc
Page 615 and 616:
PLL Passive Elements User’s Manua
Page 617 and 618:
User’s Manual U10504EJ7V0UM00 PLL
Page 619 and 620:
Coprocessor 0 Hazards User’s Manu
Page 621 and 622:
User’s Manual U10504EJ7V0UM00 Cop
Page 623 and 624:
Page 625 and 626:
Page 627 and 628:
Differences Between the VR4300, VR4
Page 629 and 630:
Differences from VR4400 The VR4300
Page 631 and 632:
B.1.4 Config Register User’s Manu
Page 633 and 634:
B.2 Differences in System Design Us
Page 635 and 636:
Table B-2 Differences in System Des
Page 637 and 638:
B.3.3 Floating-Point Unit Floating-
Page 639 and 640:
Table B-3 Other Differences * 100 M
Page 641 and 642:
Differences from VR4200 The VR4300
Page 643 and 644:
C.1.4 Cache Parity Error Exception
Page 645 and 646:
C.2.3 Package Function System inter
Page 647 and 648:
Restrictions of VR4300 User’s Man
Page 649 and 650:
Index User’s Manual U10504EJ7V0UM
Page 651 and 652:
Defining Access Types ... 62 Discar
Page 653 and 654:
Processor read request ... 301, 306
Page 655:
Facsimile Message From: Name Compan
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