User's Manual - chipdb.org

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17.2 Instruction Notation Conventions...........................................552
17.3 Load and Store Instructions....................................................553
17.4 Floating-Point Computational Instructions...........................555
17.5 FPU Instructions.......................................................................558
17.6 FPU Instruction Opcode Bit Encoding...................................613
Chapter 18 PLL Passive Elements.................................................615
Chapter 19 Coprocessor 0 Hazards...............................................619
Appendix A Differences Between the V R 4300, V R 4305,
and V R 4310......................................................................627
Appendix B Differences from V R 4400...........................................629
B.1 Differences in Software ............................................................630
B.1.1 CACHE Instruction ....................................................................630
B.1.2 Cache Parity................................................................................630
B.1.3 Status Register............................................................................630
B.1.4 Config Register...........................................................................631
B.1.5 Status of FCR31 on Occurrence of Unimplemented Operation
Exception....................................................................................631
B.1.6 Integer Zero Division .................................................................631
B.1.7 Cache Parity Error Exception.....................................................632
B.2 Differences in System Design...................................................633
B.2.1 Initialization of Processor...........................................................633
B.2.2 System Interface .........................................................................633
B.3 Other Differences......................................................................636
B.3.1 Cache Size ..................................................................................636
B.3.2 TLB.............................................................................................636
B.3.3 Floating-Point Unit.....................................................................637
B.3.4 Pipeline.......................................................................................637
B.3.5 Interrupt ......................................................................................638
B.3.6 Kernel Physical Address Segment Configuration ......................638
B.3.7 JTAG ..........................................................................................638
User’s Manual U10504EJ7V0UM00