User's Manual - chipdb.org

Chapter 1
1.4.5 System Control Coprocessor (CP0)
ISA of MIPS defines four types of coprocessors (CP0 through CP3). CP0 is an
internal system control coprocessor and supports a virtual memory system and
exception processing. CP1 is an internal floating-point unit. CP2 is reserved for
future definition. CP3 is also reserved for expansion. If the CP3 instruction is
executed, a reserved instruction exception occurs.
CP0 converts virtual addresses into physical addresses, selects an operating mode
(Kernel, supervisor, or user mode), and control exceptions. It also controls the
cache subsystem to analyze causes and return execution from error processing.
The CP0 register of the V R 4300 is the same as that of the V R 4200. Because the
V R 4300 does not have a parity check function, however, its parity error register
(26) and cache error register (27) do not practically operate. These registers are
defined to maintain compatibility with the V R 4200.
Figure 1-9 shows the CP0 register. Table 1-2 briefly explains each register. For
the details of the registers related to the virtual memory system, refer to Chapter
5 Memory Management System, and for the details of the registers used for
exception processing, refer to Chapter 6 Exception Processing.
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