User's Manual - chipdb.org

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9.3.5 Instruction Trace Support...........................................................256
9.3.6 Bootstrap Exception Vector (BEV)............................................256
9.3.7 Interrupt Enable (IE)...................................................................256
Chapter 10 Clock Interface ..............................................................257
10.1 Signal Terminology ..................................................................258
10.2 Basic System Clocks .................................................................259
10.3 System Timing Parameters......................................................263
10.3.1 Synchronization with SClock.....................................................263
10.3.2 Synchronization with MasterClock ............................................263
10.3.3 Phase-Locked Loop (PLL) .........................................................263
10.4 Low Power Mode Operation ...................................................264
10.5 Connecting Clocks to a Phase-Locked System ......................265
10.6 Connecting Clocks to a System without Phase Locking .......266
10.6.1 Connecting to a Gate-Array Device ...........................................266
10.6.2 Connecting to a CMOS Discrete Device....................................269
Chapter 11 Cache Memory...............................................................273
11.1 Memory Organization..............................................................274
11.2 Cache Organization..................................................................275
11.2.1 Organization of the Instruction Cache (I-Cache) .......................276
11.2.2 Organization of the Data Cache (D-Cache)................................277
11.2.3 Accessing the Caches .................................................................278
11.3 Cache Operations .....................................................................279
11.3.1 Cache Write Policy.....................................................................280
11.3.2 Data Cache Line Replacement ...................................................280
11.3.3 Instruction Cache Line Replacement..........................................282
11.4 Cache States ..............................................................................283
11.5 Cache State Transition Diagrams ...........................................283
11.5.1 Data Cache State Transition .......................................................284
11.5.2 Instruction Cache State Transition .............................................285
11.6 Manipulation of the Caches by an External Agent ...............285
User’s Manual U10504EJ7V0UM00