User's Manual - chipdb.org

22
LIST OF FIGURES (3/6)
Figure No. Title Page
6-9 WatchLo and WatchHi Registers ..............................................175
6-10 XContext Register .........................................................................176
6-11 PErr Register .................................................................................178
6-12 CacheErr Register ........................................................................178
6-13 ErrorEPC Register .......................................................................179
6-14 General Purpose Exception Handler .......................................201
6-15 TLB/XTLB Miss Exception Handler .......................................203
6-16 Cold Reset, Soft Reset & NMI Exception Handler ..............205
7-1 FPU Registers .................................................................................209
7-2 Control/Status Register Bit Assignments ................................211
7-3 Control/Status Register (FCR31) Cause, Enable,
and Flag Bit Fields ........................................................................212
7-4 Implementation/Revision Register ...........................................216
7-5 Single-Precision Floating-Point Format ..................................217
7-6 Double-Precision Floating-Point Format ................................217
7-7 32-Bit Fixed-Point Format ..........................................................220
7-8 64-Bit Fixed-Point Format ..........................................................220
7-9 DC-to-EX Hardware Interlock Bypass ...................................231
8-1 FCR31 Cause/Enable/Flag Bits .................................................237
9-1 Power-ON Reset .............................................................................252
9-2 Cold Reset ........................................................................................252
9-3 Soft Reset..........................................................................................253
10-1 Signal Transitions ..........................................................................258
10-2 Clock-to-Q Delay ...........................................................................258
10-3 When Frequency Ratio of MasterClock to
PClock is 1:1.5 ................................................................................261
10-4 When Frequency Ratio of MasterClock to
PClock is 1:2 ...................................................................................262
10-5 Phase-Locked System ...................................................................265
User’s Manual U10504EJ7V0UM00