User's Manual - chipdb.org

20
LIST OF FIGURES (1/6)
Figure No. Title Page
1-1 Internal Block Diagram .................................................................34
1-2 CPU Registers ..................................................................................38
1-3 CPU Instruction Formats .............................................................39
1-4 Big-Endian Byte Ordering ............................................................41
1-5 Little-Endian Byte Ordering ........................................................41
1-6 Big-Endian Data in a Doubleword .............................................42
1-7 Little-Endian Data in a Doubleword .........................................42
1-8 Misaligned Word Addressing .......................................................43
1-9 CP0 Registers ...................................................................................45
3-1 CPU Instruction Formats .............................................................60
3-2 Byte Access within a Doubleword ...............................................63
4-1 Pipeline Stages .................................................................................90
4-2 Instruction Execution in the Pipeline ........................................91
4-3 Pipeline Operations ........................................................................92
4-4 Branch Delay ....................................................................................94
4-5 Add Instruction Pipeline Operations .........................................97
4-6 Jump and Link Register Instruction Pipeline Operations ...98
4-7 Branch on Equal Instruction Pipeline Operations ................99
4-8 Trap if Less Than Instruction Pipeline Operations .............100
4-9 Load Word Instruction Pipeline Operations .........................101
4-10 Store Word Instruction Pipeline Operations .........................102
4-11 Interlocks, Exceptions, and Faults ...........................................103
4-12 Correspondence of Pipeline Stage to Interlock and
Exception Condition .....................................................................104
4-13 Instruction TLB Miss Interlock ................................................107
4-14 Example of an Instruction Cache Busy Interlock ................108
4-15 Example of a Multicycle Instruction Interlock .....................109
4-16 Example of a Load Interlock .....................................................110
4-17 Example of a Data Cache Miss Followed by a Load
Interlock ..........................................................................................112
User’s Manual U10504EJ7V0UM00