1993_Motorola_Linear_Interface_ICs_Vol_2.pdf

MC10319
TIMING CHARACTERISTICS (TA = 25°C, VCC = +5.0 V, VEE = -5.2 V, VRT = +1.0 V, VRB = -1.0 V,
See System Timing Diagram.)
Parameter Symbol Min Typ
INPUTS
Min Clock Pulse Width - High tCKH -
Min Clock Pulse Width - Low tCKL -
Max Clock Rise, Fall Time tR,F -
Clock Frequency fCLK 0
OUTPUTS
New Data Valid from Clock Low tCKDV -
Aperture Delay tAD -
Hold Time tH -
Data High to 3-State from Enable Low' tEHZ -
Data Low to 3-State from Enable Low' tELZ -
Data High to 3·State from Enable High' tEHZ -
Data Low to 3-State from Enable High' tELZ -
Valid Data from Enable High (Pin 20 = 0 V)' tEDV -
Valid Data from Enable Low (Pin 19 = 5.0 V)' tEDV -
Output Transition Time' (10%-90%) ttr -
*See FIgure 2 for output loadtng.
PIN DESCRIPTIONS
Symbol
Pin
L,P Suffix OW Suffix Description
VRM 1 1 The midpoint of the reference resistor ladder. Bypassing can
be done at this point to improve performance at high
frequencies.
GND 2,12 2,13,17
16,22 18,25,26
OVR 3 3
D7-DIIl 4-10,21 4-10,24
VCC(D) 11,17 11,12
19,20
VEE 13 14
Vin 14 15
VCC(A) 15 16
CLK 18 21
EN 19 22
EN 20 23
VRB 23 27
VRT 24 28
Digital ground. The pins should be connected directly together,
and through a low impedance path to the power supply.
Overrange output. Indicates Vin is more positive than VRT 112
LSB. This output does not have 3-state capability.
Digital Outputs. 07 (Pin 4) is the MSB. Dill (Pin 21 or 24) is the
LSB. LSTTL compatible with 3·state capability.
Power supply for the digital section. +5.0 V, ± 10% required.
Reference to digital ground.
Negative Power supply. Nominally - 5.2 V, it can range from
-3.0to -6.0 V, and must be more negative than VRB by >1.3 V.
Reference to analog gnd.
Signal voltage input. This voltage is compared to the reference
to generate a digital equivalent. Input impedance is nominally
16-33K in parallel with 36 pF.
Power supply for the analog section. + 5.0 V, ± 10% required.
Reference to analog ground.
Clock input. TTL compatible.
Enable input. TTL compatible, a logic 1 (and EN at a logic 0)
enables the data outputs. A logic 0 puts the outputs in a 3-state
mode.
Enable input. TTL compatible, a logic 0 (and EN at a logic 1)
enables the data outputs. A logic 1 puts the outputs in a 3-state
mode.
The bottom (most negative point) of the internal reference
resistor ladder.
The top (most positive point) of the internal reference resistor
ladder.
MOTOROLA L1NEARIINTERFACE ICs DEVICE DATA
6-30
5.0
15
100
30
19
4.0
6.0
27
18
32
18
15
16
8.0
Max Unit
- ns
- ns
- ns
25 MHz
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns