Bias Circuit

But Id1 = –Id4 and Id4 is mirrored as Id5, which leads to Id5 = –Id1. This assumes that M4 and M5
are identical. Thus,
Equation 14.13
All signal drain currents are defined as positive into the respective drains.
The output currents summed at the output node, Vo, are (defined positive into the node)
Equation 14.14
The result is valid for vO = VO or Vo = 0, as stipulated above. One could imagine attaching a dc
supply exactly equal to VO at the output node. In this case, the output current could readily
flow into the node according to (14.14).
For the opposite extreme of having an open circuit at the output, as in Fig. 14.3, the currents
Id2 and Id5 are dependent on vD2 = vD5 = vO. The deviation of Io from (14.14) is, as usual, taken
care of by including the effect of the output resistance at the output node.
The output resistance is somewhat complicated by feedback effects, which are inherent in this
circuit. For assessing the circuit output resistance, a signal circuit is shown in Fig. 14.4 with a
test voltage, Vo, applied at the output with both inputs grounded. Resulting currents Id2 and Id5
will be considered separately and will be superimposed.
Figure 14.4. Signal (linear) circuit for determining the output
resistance at the drains of M2 and M5. Currents shown are associated
with the assessment of the output resistance associated with M2 only.
The bias transistor (M11) output resistance is neglected.
The currents indicated in Fig. 14.4 are for the case of Id2 of M2. Looking back into the drain of
M2, the output resistance is affected by emitter degeneration because of the resistance 1/gm1
between the emitter of M2 and ground. That is, the resistance looking back into the emitter of
M1 is 1/gm1. Thus, the resistance looking only back into M2 is 2rds2. However, Id2 feeds through
and around the loop composed of M2, M1, M4, and M5 such that the total current flowing into