Bias Circuit

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Laboratory Project A. Communicating with the <strong>Circuit</strong> Board Using the DAQ PA.1 Sending and Receiving Voltages with the Sending and Receiving VIs PA.2 Sending and Receiving Voltages from the Front Panel PA.3 Plotting Measured Samples PA.4 Using the Autoranging Voltmeter PA.5 Observing the Oscilloscope Output Graph PA.6 Discrete Output Voltage from the DAQ PA.7 Discrete Input Voltage from the <strong>Circuit</strong> Board PA.8 Using the Simultaneous Sending/Receiving Function Diagram Front Panel TABLE PA.1 Tools Palette Shift/Right Click Functions Palette Right Click–Stickpin to hold Menu Sequence: Window>>Show Functions Palette Tools Palette Shift/Right Click Controls Palette Right Click–Stickpin to hold Menu Sequence: Windows>>Show Controls Palette
PA.1 Sending and Receiving Voltages with the Sending and Receiving VIs • Connect Chan0_in directly to Chan0_out on the circuit board or connector block. Double Click on both of the icons in the Diagram of Measure.vi (initial version) to bring up the VI Front Panels. These are AO Update Channel.vi and AI Acquire Waveform.vi. Set both VIs to your device number for your DAQ card and to channel 0 (using the Operating Tool or finger). Set the number of samples to 10, for example. Set the high limit and low limit in AI Acquire Waveform.vi to default 0.0 V. Obtain a default status of the settings in both VIs. For this, go to menu Operate>>Make Current Values Default. • In the Front Panel of AO Update Channel.vi, set in a voltage of 1 V or similar (using the Operating Tool). Run the VI, AO Update Channel.vi. To run the VI, use menu sequence Operate>> Run (or, preferred, Ctrl/R). Then run AI Acquire Waveform.vi and note the voltage read (waveform array Digital Indicator). Click on the up and down arrows by the Y to scroll through more data points. • Verify that that send and receive are consistent. Try some other voltages. Note the maximum allowed is the highlimit, 10 V. Close the send and receive VIs. Leave Measure.vi open.
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Copyright Library of Congress Catal
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National Improvements | Virtual Ins
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formulations, the results from Math
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Hardware and Software Requirements
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Chan0_out Pin 21 Chan0_in Pin 68 Gn
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LabVIEW VI Libraries and Project an
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1.1 Resistor Voltage Divider and MO
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1.3 Frequency Response of the Ampli
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At f = flo, . This, by definition,
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1.5 Exercises and Projects Project
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2.1 BJT and MOSFET Schematic Symbol
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2.2 Fundamentals of Signal Amplific
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2.3 Basic NMOS Common-Source Amplif
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Using (2.4), (2.5), (2.9), and (2.1
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Unit 3. Characterization of MOS Tra
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In electronic circuit applications,
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The output-characteristic equation
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Equation 3.11 From the data measure
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The input circuit loop equation (Fi
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which leads to the result (3.5), re
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Unit 4. Signal Conductance Paramete
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4.2 Transistor Variable Incremental
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4.3 Transconductance Parameter The
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4.4 Body-Effect Transconductance Pa
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4.5 Output Conductance Parameter Th
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With a 1 - V drop across RS and a 5
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By the nature of the load-line func
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Unit 5. Common-Source Amplifier Sta
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5.2 Amplifier Voltage Gain This dc
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etween the drain and source of the
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5.3 Linearity of the Gain of the Co
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where av Vds/Vgs and where the appr
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is attached directly to the gate. B
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5.5 Design of a Basic Common-Source
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= VGSo - Vtno at the high and low e
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RG can be selected somewhat arbitra
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6.1 Grounded-Source Amplifier: Coup
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and Equation 6.6 Note that the "RC"
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6.4 Load Coupling Capacitor The com
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6.5 Summary of Equations MOSFET cou
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Unit 7. MOSFET Source-Follower Buff
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7.2 Source-Follower Voltage Transfe
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7.3 Body Effect and Source-Follower
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7.4 Summary of Equations Threshold
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Unit 8. MOSFET Differential Amplifi
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8.2 DC Imbalances In a real transis
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8.3 Signal Voltage Gain of the Idea
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8.4 Effect of the Bias Resistor on
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8.5 Differential Voltage Gain Suppo
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8.7 Voltage Gains Including Transis
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8.7.2 Common-Gate Amplifier Stage T
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with RD1 = RD2 and gm1 = gm2. In th
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It follows that the gain for the in
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8.9 Amplifier Gain with Differentia
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8.11 Summary of Equations Rs = Ris2
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9.1 Basic Current Source An example
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9.2 Current Source with Source Dege
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If the magnitude of the voltage acr
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Any slight possible difference in
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Unit 10. Common-Source Amplifier wi
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10.2 Signal Voltage Gain The expres
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10.3 Summary of Equations Output dr
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Unit 11. Operational Amplifiers wit
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11.1.1 Voltage Gain of the Noninver
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This expression can be manipulated
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11.3 Operational Amplifier Offset I
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where the approximation usually app
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where Avo is the amplifier gain at
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12.1 Operational Amplifier Integrat
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This demonstrates that for the circ
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with a steady-state value of Vop. A
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Equation 12.25 A good estimate come
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13.1 Combining NMOS and PMOS Circui
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13.3 Stabilization of Signal Gain a
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An estimate of the new output volta
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This produces (9.9) from Ro = Vo/Io
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Equation 13.13 where 13.12 has been
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The open-loop transconductance is G
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Unit 14. Development of a Basic CMO
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14.2 Current-Source Output Resistan
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14.3 Current-Source Load for the Co
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14.4 Current-Source Load for the Di
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the node (exclusive of the separate
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14.5 Two-Stage Amplifier with Curre
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14.6 Output Buffer Stage It is evid
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Suppose that ID6 = 400 µA, W6 = 50
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Av and Ro are calculated once, usin
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Since the source follower of M1 has
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14.9 Summary of Equations CMRR = 1
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Unit A. Communicating with the Circ
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Place AI Acquire Waveform.vi in the
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Click from the Front Panel or Diagr
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Now go to the Diagram (under Menu W
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To complete connections to the term
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Now use the Edit Text Tool to edit
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on the left in the diagram . The Wh
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Figure A.15. Frame of Sequence Stru
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The transition regions are nonabrup
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during the oscilloscope measurement
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Unit B. Characterization of the Bip
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junction diodes, the current is lar
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common to the input and output and
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B.2 Base-Width Dependence on Juncti
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Figure B.8. Diodelike characteristi
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The minus sign comes from having as
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Figure B.10. Circuit for measuring
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B.5 Output Characteristics of BJT i
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After measuring the output characte
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B.6 SPICE Solution for IC versus VC
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B.7 Collector-Emitter Voltage and C
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B.8 DC as a Function of Collector C
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B.10 Summary of Equations Common-em
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Unit C. Common-Emitter Amplifier St
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The equation set above has three un
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The output-resistance parameter, ro
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of βDC as possible. Signal paramet
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Equation C.17 We note that the magn
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C.4 Accuracy of Transistor Gain Mea
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C.5 Effect of Finite Slope of the T
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It follows that for this case, f3dB
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C.7 Common-Emitter Amplifier with A
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Equation C.41 where IC IC(VCE), tha
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Applied voltage Vo sums up to Equat
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C.7.3 DC (Bias) of the NPN - PNP Am
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where Equation C.58 and Equation C.
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Equation C.67 The result is signifi
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The following form of the result pr
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This is equivalent to a unity-gain
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C.11 Summary of Circuit Equations B
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C.12 Exercises and Projects Project
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P1.1 Resistor Voltage-Divider Measu
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• Place AO Update Channel.vi in F
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• (Optional) To install the circu
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Procedure • Set your value of RG2
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• In the Diagram, we will add Get
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P1.4 Resistor Voltage Divider with
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• Now move the capacitor C2 = C1
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P2.1 NMOS Common-Source Circuit wit
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• In the Diagram (below), place,
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P2.2 NMOS Common-Source Amplifier w
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P2.3 Amplifier with Signal and Gain
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• Connect to FG1Chan.vi, the vari
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P3.1 SPICE Parameters and Pin Diagr
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P3.3 PMOS Transistor Use pins 6 (ga
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Procedure • Run PMOSlinear.vi and
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Procedure • Run PMOSparsub.vi wit
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Procedure • Run PMOSparam.vi to r
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Active Region Procedure • Install
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Laboratory Project 4. Characterizat
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P4.2 NMOS Transistor Use CD4007 pin
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P4.4 NMOS Parameters from the Trans
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P4.5 NMOS Lambda from the Transfer
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P4.6 NMOS Gamma SubVI Components No
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• Set RS. With NMOSgamsub.vi open
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• A file can be obtained from the
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P5.1 SPICE Equations and Pin Diagra
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P5.3 Amplifier Gain at One Bias Cur
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P5.4 Amplifier Gain versus Bias Cur
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Laboratory Project 6. PMOS Common-
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P6.2 SPICE PMOS and Circuit Equatio
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P6.4 Amplifier Gain LabVIEW Computa
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P6.5 Amplifier Frequency Response P
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P7.1 Chip Diagram and SPICE Equatio
Page 346 and 347: P7.3 Amplifier Gain at Optimum Bias
Page 348 and 349: P7.4 Optimum Bias Stability Test
Page 350 and 351: P7.5 Amplifier Frequency Response P
Page 352 and 353: Laboratory Project 8. NMOS Source-
Page 354: P8.2 Source-Follower DC Evaluation
Page 357 and 358: available for the next VI. It is us
Page 359 and 360: Laboratory Project 9. MOSFET Differ
Page 361 and 362: P9.2 DC Evaluation of the Single-Po
Page 363 and 364: P9.3 Determination of the PMOS Para
Page 365 and 366: Gains will be obtained from the gra
Page 367 and 368: • Run SweepSim.vi to obtain the d
Page 369 and 370: Laboratory Project 10. Current Mirr
Page 371 and 372: P10.2 Evaluation of the Current-Sou
Page 373 and 374: P10.4 Evaluation of the Bias Setup
Page 376 and 377: Laboratory Project 11. Operational
Page 378 and 379: P11.2 Bias Circuit Setup 1 Offset N
Page 380 and 381: P11.3 Opamp Offset Voltage Componen
Page 382 and 383: P11.4 Evaluation of the Bias Balanc
Page 384 and 385: VOH • Reset the Chan0_out Range,
Page 386 and 387: P11.6 Evaluation of the Gain with S
Page 388 and 389: P11.7 Determination of the Opamp Fr
Page 390 and 391: Laboratory Project 12. Operational
Page 392 and 393: P12.2 Opamp Integrator Components R
Page 394 and 395: Procedure • Turn off the power su
Page 398: PA.2 Sending and Receiving Voltages
Page 401 and 402: Bipolar TABLE PA.2 0 to +5V 1.22 mV
Page 403 and 404: PA.5 Observing the Oscilloscope Out
Page 405 and 406: of the DAC. The steps are 2.44 mV f
Page 407 and 408: • The example here illustrates th
Page 409 and 410: Laboratory Project B. Characterizat
Page 411 and 412: PB.2 SPICE Equations SPICE Equation
Page 413 and 414: parameters nF and IS. • Connect C
Page 415 and 416: PB.4 DC versus the Collector Curren
Page 417 and 418: • Now open VI, IC_VCE.vi. Set the
Page 419 and 420: Laboratory Project C1. NPN Common-
Page 421 and 422: PC.2 DC Circuit Setup and Parameter
Page 423 and 424: PC.3 Amplifier Gain at One Bias Cur
Page 425 and 426: PC.4 Amplifier Gain versus Bias Cur
Page 427 and 428: • Run FreqResp.vi. Verify that in
Page 429 and 430: PC.6 SPICE Equations and Pin Diagra
Page 431 and 432: • Determine the value of VAF spec
Page 433 and 434: • Set the Run Mode switch to Set
Page 435: • Now reset VCC(init) and VBB(ini
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Bias Circuit

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