Bias Circuit

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Procedure • Run AmpP2.2.vi with VDD set at 6 V to obtain VGS of about 2 V (due to RG1 2RG2). Rerun and adjust VDD to obtain VDS equal to about one-half of VDD. Note that decreasing VDD raises VDS toward VDD. Default and save the Front Panel for the Mathcad evaluation.
P2.3 Amplifier with Signal and Gain Measurement Programming Exercise 2.3 follows below. (Advanced-Optional) Procedure • Move the bottom of RG2 from ground to Chan1_out. The VI will send out a sine-wave signal via this channel with peak Vs. Set Chan0_out (VDD) as in the circuit for P2.2 above (for VDS VDD/2). • Run AmpP2.3.vi (Project02.llb) for various values of Vs. Re-set for a Vo peak of about 1V (VDS/3). Note the gains, which are Vo/Vs and Vo/Vg. Verify that the gain from the source is about two-thirds of the gain the gate, based on the selection (ratio) of the gate bias resistors. Default and save the Front Panel for the Mathcad evaluation. Programming Exercise 2.3 • Make a copy of AmpP2.2.vi with a new name. • Go to the Diagram and delete all except Control and Indicator terminals. • Install a Sequence Structure in the Diagram (below). In the first Frame, install AO Update Channel.vi. (Functions>>Data Acquisition>>Analog Output.)
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Copyright Library of Congress Catal
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National Improvements | Virtual Ins
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formulations, the results from Math
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Hardware and Software Requirements
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Chan0_out Pin 21 Chan0_in Pin 68 Gn
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LabVIEW VI Libraries and Project an
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1.1 Resistor Voltage Divider and MO
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1.3 Frequency Response of the Ampli
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At f = flo, . This, by definition,
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1.5 Exercises and Projects Project
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2.1 BJT and MOSFET Schematic Symbol
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2.2 Fundamentals of Signal Amplific
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2.3 Basic NMOS Common-Source Amplif
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Using (2.4), (2.5), (2.9), and (2.1
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Unit 3. Characterization of MOS Tra
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In electronic circuit applications,
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The output-characteristic equation
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Equation 3.11 From the data measure
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The input circuit loop equation (Fi
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which leads to the result (3.5), re
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Unit 4. Signal Conductance Paramete
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4.2 Transistor Variable Incremental
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4.3 Transconductance Parameter The
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4.4 Body-Effect Transconductance Pa
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4.5 Output Conductance Parameter Th
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With a 1 - V drop across RS and a 5
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By the nature of the load-line func
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Unit 5. Common-Source Amplifier Sta
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5.2 Amplifier Voltage Gain This dc
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etween the drain and source of the
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5.3 Linearity of the Gain of the Co
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where av Vds/Vgs and where the appr
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is attached directly to the gate. B
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5.5 Design of a Basic Common-Source
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= VGSo - Vtno at the high and low e
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RG can be selected somewhat arbitra
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6.1 Grounded-Source Amplifier: Coup
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and Equation 6.6 Note that the "RC"
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6.4 Load Coupling Capacitor The com
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6.5 Summary of Equations MOSFET cou
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Unit 7. MOSFET Source-Follower Buff
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7.2 Source-Follower Voltage Transfe
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7.3 Body Effect and Source-Follower
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7.4 Summary of Equations Threshold
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Unit 8. MOSFET Differential Amplifi
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8.2 DC Imbalances In a real transis
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8.3 Signal Voltage Gain of the Idea
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8.4 Effect of the Bias Resistor on
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8.5 Differential Voltage Gain Suppo
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8.7 Voltage Gains Including Transis
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8.7.2 Common-Gate Amplifier Stage T
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with RD1 = RD2 and gm1 = gm2. In th
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It follows that the gain for the in
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8.9 Amplifier Gain with Differentia
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8.11 Summary of Equations Rs = Ris2
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9.1 Basic Current Source An example
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9.2 Current Source with Source Dege
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If the magnitude of the voltage acr
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Any slight possible difference in
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Unit 10. Common-Source Amplifier wi
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10.2 Signal Voltage Gain The expres
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10.3 Summary of Equations Output dr
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Unit 11. Operational Amplifiers wit
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11.1.1 Voltage Gain of the Noninver
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This expression can be manipulated
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11.3 Operational Amplifier Offset I
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where the approximation usually app
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where Avo is the amplifier gain at
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12.1 Operational Amplifier Integrat
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This demonstrates that for the circ
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with a steady-state value of Vop. A
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Equation 12.25 A good estimate come
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13.1 Combining NMOS and PMOS Circui
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13.3 Stabilization of Signal Gain a
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An estimate of the new output volta
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This produces (9.9) from Ro = Vo/Io
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Equation 13.13 where 13.12 has been
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The open-loop transconductance is G
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Unit 14. Development of a Basic CMO
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14.2 Current-Source Output Resistan
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14.3 Current-Source Load for the Co
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14.4 Current-Source Load for the Di
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the node (exclusive of the separate
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14.5 Two-Stage Amplifier with Curre
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14.6 Output Buffer Stage It is evid
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Suppose that ID6 = 400 µA, W6 = 50
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Av and Ro are calculated once, usin
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Since the source follower of M1 has
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14.9 Summary of Equations CMRR = 1
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Unit A. Communicating with the Circ
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Place AI Acquire Waveform.vi in the
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Click from the Front Panel or Diagr
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Now go to the Diagram (under Menu W
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To complete connections to the term
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Now use the Edit Text Tool to edit
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on the left in the diagram . The Wh
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Figure A.15. Frame of Sequence Stru
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The transition regions are nonabrup
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during the oscilloscope measurement
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Unit B. Characterization of the Bip
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junction diodes, the current is lar
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common to the input and output and
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B.2 Base-Width Dependence on Juncti
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Figure B.8. Diodelike characteristi
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The minus sign comes from having as
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Figure B.10. Circuit for measuring
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B.5 Output Characteristics of BJT i
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After measuring the output characte
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B.6 SPICE Solution for IC versus VC
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B.7 Collector-Emitter Voltage and C
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B.8 DC as a Function of Collector C
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B.10 Summary of Equations Common-em
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Unit C. Common-Emitter Amplifier St
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The equation set above has three un
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The output-resistance parameter, ro
Page 246 and 247: of βDC as possible. Signal paramet
Page 248 and 249: Equation C.17 We note that the magn
Page 250 and 251: C.4 Accuracy of Transistor Gain Mea
Page 252 and 253: C.5 Effect of Finite Slope of the T
Page 254 and 255: It follows that for this case, f3dB
Page 256 and 257: C.7 Common-Emitter Amplifier with A
Page 258 and 259: Equation C.41 where IC IC(VCE), tha
Page 260 and 261: Applied voltage Vo sums up to Equat
Page 262 and 263: C.7.3 DC (Bias) of the NPN - PNP Am
Page 264 and 265: where Equation C.58 and Equation C.
Page 266 and 267: Equation C.67 The result is signifi
Page 268 and 269: The following form of the result pr
Page 270 and 271: This is equivalent to a unity-gain
Page 272 and 273: C.11 Summary of Circuit Equations B
Page 274 and 275: C.12 Exercises and Projects Project
Page 276 and 277: P1.1 Resistor Voltage-Divider Measu
Page 278 and 279: • Place AO Update Channel.vi in F
Page 280 and 281: • (Optional) To install the circu
Page 282 and 283: Procedure • Set your value of RG2
Page 284 and 285: • In the Diagram, we will add Get
Page 286 and 287: P1.4 Resistor Voltage Divider with
Page 288 and 289: • Now move the capacitor C2 = C1
Page 290 and 291: P2.1 NMOS Common-Source Circuit wit
Page 292 and 293: • In the Diagram (below), place,
Page 295: P2.2 NMOS Common-Source Amplifier w
Page 299 and 300: • Connect to FG1Chan.vi, the vari
Page 301 and 302: P3.1 SPICE Parameters and Pin Diagr
Page 303 and 304: P3.3 PMOS Transistor Use pins 6 (ga
Page 305 and 306: Procedure • Run PMOSlinear.vi and
Page 307 and 308: Procedure • Run PMOSparsub.vi wit
Page 309 and 310: Procedure • Run PMOSparam.vi to r
Page 311 and 312: Active Region Procedure • Install
Page 313 and 314: Laboratory Project 4. Characterizat
Page 315 and 316: P4.2 NMOS Transistor Use CD4007 pin
Page 317 and 318: P4.4 NMOS Parameters from the Trans
Page 319 and 320: P4.5 NMOS Lambda from the Transfer
Page 321 and 322: P4.6 NMOS Gamma SubVI Components No
Page 323 and 324: • Set RS. With NMOSgamsub.vi open
Page 325 and 326: • A file can be obtained from the
Page 327 and 328: P5.1 SPICE Equations and Pin Diagra
Page 330 and 331: P5.3 Amplifier Gain at One Bias Cur
Page 332 and 333: P5.4 Amplifier Gain versus Bias Cur
Page 334 and 335: Laboratory Project 6. PMOS Common-
Page 336 and 337: P6.2 SPICE PMOS and Circuit Equatio
Page 339 and 340: P6.4 Amplifier Gain LabVIEW Computa
Page 341 and 342: P6.5 Amplifier Frequency Response P
Page 343 and 344: P7.1 Chip Diagram and SPICE Equatio
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P7.3 Amplifier Gain at Optimum Bias
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P7.4 Optimum Bias Stability Test
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P7.5 Amplifier Frequency Response P
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Laboratory Project 8. NMOS Source-
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P8.2 Source-Follower DC Evaluation
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available for the next VI. It is us
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Laboratory Project 9. MOSFET Differ
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P9.2 DC Evaluation of the Single-Po
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P9.3 Determination of the PMOS Para
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Gains will be obtained from the gra
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• Run SweepSim.vi to obtain the d
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Laboratory Project 10. Current Mirr
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P10.2 Evaluation of the Current-Sou
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P10.4 Evaluation of the Bias Setup
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Laboratory Project 11. Operational
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P11.2 Bias Circuit Setup 1 Offset N
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P11.3 Opamp Offset Voltage Componen
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P11.4 Evaluation of the Bias Balanc
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VOH • Reset the Chan0_out Range,
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P11.6 Evaluation of the Gain with S
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P11.7 Determination of the Opamp Fr
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Laboratory Project 12. Operational
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P12.2 Opamp Integrator Components R
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Procedure • Turn off the power su
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Laboratory Project A. Communicating
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PA.2 Sending and Receiving Voltages
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Bipolar TABLE PA.2 0 to +5V 1.22 mV
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PA.5 Observing the Oscilloscope Out
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of the DAC. The steps are 2.44 mV f
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• The example here illustrates th
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Laboratory Project B. Characterizat
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PB.2 SPICE Equations SPICE Equation
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parameters nF and IS. • Connect C
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PB.4 DC versus the Collector Curren
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• Now open VI, IC_VCE.vi. Set the
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Laboratory Project C1. NPN Common-
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PC.2 DC Circuit Setup and Parameter
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PC.3 Amplifier Gain at One Bias Cur
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PC.4 Amplifier Gain versus Bias Cur
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• Run FreqResp.vi. Verify that in
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PC.6 SPICE Equations and Pin Diagra
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• Determine the value of VAF spec
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• Set the Run Mode switch to Set
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• Now reset VCC(init) and VBB(ini
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