Bias Circuit

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Click from the Front Panel or Diagram. Figure A.3. LabVIEW VI Diagram with the addition of output channel VI AO Update Channel.vi. The two VIs represented by the icons can be opened with Right Click and open Front Panel or with Double Click. Project PA.1 Sending and Receiving Voltages with the Sending and Receiving VIs (Measure.vi, version 1) A.1.2 Programming Exercise: Using a Sequence Structure The two VIs represented by the icons of the Diagram are subVIs of Measure.vi. That is, they will run when we run Measure.vi. In this case, it is necessary that they execute in the proper order. For example, we would want to send out the voltage before reading the response. For ensuring proper execution order, install a Sequence Structure as shown in Fig. A.4. Obtain the Sequence Structure from the Diagram under the menu series Functions>>Structures>>Sequence. Recall that to obtain the Functions Palette, Right Click on the Diagram. Figure A.4. LabVIEW VI Diagram with Sequence Structure. This Structure executes in order of index at the top of the Frames. Frame 1 shown contains the VI for reading voltage. Frame 0 contains the VI for sending voltage. Click on arrows to move through Frames. Also shown is the Structures Palette under Functions and the process of adding a frame.
Initially, the Sequence Structure is too small. To enlarge, get the Positioning Tool (arrow) by pressing the Space Bar, by sequencing through the Tools with Tab, or by using Shift/Right Click to bring up the Tools Palette. Position the Tool at the lower-right-hand corner of the Sequence Structure, Left Click, and drag to enlarge the Structure. Right Click on the edge of the Frame of the Sequence Structure and go to Add Frame After (Fig. A.4). The result will be two Frames with index 0 and index 1. Now place (e.g., drag) the send and receive VIs into Frame 0 and Frame 1, respectively. Left Click on the left and right arrows at the top of the Sequence Structure to move between Frames. The result will be as shown in Fig. A.4. The Diagram shows Frame 1. The program will execute the VI in numerical Frame order. Thus, the output voltage will always be sent before the input channel attempts to read. A.1.3 Programming Exercise: Digital Controls and Digital Indicators The Front Panel of Measure.vi will now be configured to permit assigning the voltage to be sent out and reading the input voltage from the Front Panel. The Front Panel of the new configuration is shown in Fig. A.5. From the Front Panel and then from the Controls Palette, go to Controls>>Numeric (Fig. A.5), and from this selection, get a Digital Control and a Digital Indicator. You might want to color the Front Panel. For this, Shift/Right Click and get the Coloring Tool from the bottom of the Palette. Then, with the Coloring Tool, Right Click on the Front Panel and pick a color. You can also color the Diagram. Change the labels over the Digital Control and Digital Indicator using the Edit Text Tool (Fig. A.5). Obtain the Tools Palette with Shift/Right Click and the Edit Text Tool. The labels are defaulted as Numeric. Use the Edit Text Tool from the Tools Palette to relabel as in the example (or similar). Figure A.5. Front Panel with addition of Digital Control (send) and Digital Indicator (receive). These are obtained with a Right Click on Front Panel for Controls Palette and then Numeric and Digital Control and Digital Indicator. Also shown is the Edit Text Tool for changing the labels on the Controls from the default Numeric.
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Copyright Library of Congress Catal
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National Improvements | Virtual Ins
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formulations, the results from Math
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Hardware and Software Requirements
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Chan0_out Pin 21 Chan0_in Pin 68 Gn
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LabVIEW VI Libraries and Project an
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1.1 Resistor Voltage Divider and MO
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1.3 Frequency Response of the Ampli
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At f = flo, . This, by definition,
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1.5 Exercises and Projects Project
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2.1 BJT and MOSFET Schematic Symbol
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2.2 Fundamentals of Signal Amplific
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2.3 Basic NMOS Common-Source Amplif
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Using (2.4), (2.5), (2.9), and (2.1
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Unit 3. Characterization of MOS Tra
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In electronic circuit applications,
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The output-characteristic equation
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Equation 3.11 From the data measure
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The input circuit loop equation (Fi
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which leads to the result (3.5), re
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Unit 4. Signal Conductance Paramete
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4.2 Transistor Variable Incremental
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4.3 Transconductance Parameter The
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4.4 Body-Effect Transconductance Pa
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4.5 Output Conductance Parameter Th
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With a 1 - V drop across RS and a 5
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By the nature of the load-line func
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Unit 5. Common-Source Amplifier Sta
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5.2 Amplifier Voltage Gain This dc
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etween the drain and source of the
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5.3 Linearity of the Gain of the Co
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where av Vds/Vgs and where the appr
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is attached directly to the gate. B
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5.5 Design of a Basic Common-Source
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= VGSo - Vtno at the high and low e
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RG can be selected somewhat arbitra
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6.1 Grounded-Source Amplifier: Coup
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and Equation 6.6 Note that the "RC"
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6.4 Load Coupling Capacitor The com
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6.5 Summary of Equations MOSFET cou
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Unit 7. MOSFET Source-Follower Buff
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7.2 Source-Follower Voltage Transfe
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7.3 Body Effect and Source-Follower
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7.4 Summary of Equations Threshold
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Unit 8. MOSFET Differential Amplifi
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8.2 DC Imbalances In a real transis
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8.3 Signal Voltage Gain of the Idea
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8.4 Effect of the Bias Resistor on
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8.5 Differential Voltage Gain Suppo
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8.7 Voltage Gains Including Transis
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8.7.2 Common-Gate Amplifier Stage T
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with RD1 = RD2 and gm1 = gm2. In th
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It follows that the gain for the in
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8.9 Amplifier Gain with Differentia
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8.11 Summary of Equations Rs = Ris2
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9.1 Basic Current Source An example
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9.2 Current Source with Source Dege
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If the magnitude of the voltage acr
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Any slight possible difference in
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Unit 10. Common-Source Amplifier wi
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10.2 Signal Voltage Gain The expres
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10.3 Summary of Equations Output dr
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Unit 11. Operational Amplifiers wit
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11.1.1 Voltage Gain of the Noninver
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This expression can be manipulated
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11.3 Operational Amplifier Offset I
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where the approximation usually app
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where Avo is the amplifier gain at
Page 147 and 148: 11.7 Exercises and Projects Project
Page 149 and 150: 12.1 Operational Amplifier Integrat
Page 151 and 152: This demonstrates that for the circ
Page 153 and 154: with a steady-state value of Vop. A
Page 155 and 156: Equation 12.25 A good estimate come
Page 157 and 158: 12.4 Exercises and Projects Project
Page 159 and 160: 13.1 Combining NMOS and PMOS Circui
Page 161 and 162: 13.3 Stabilization of Signal Gain a
Page 163 and 164: An estimate of the new output volta
Page 165 and 166: This produces (9.9) from Ro = Vo/Io
Page 167 and 168: Equation 13.13 where 13.12 has been
Page 169 and 170: The open-loop transconductance is G
Page 171 and 172: Unit 14. Development of a Basic CMO
Page 173 and 174: 14.2 Current-Source Output Resistan
Page 175 and 176: 14.3 Current-Source Load for the Co
Page 177 and 178: 14.4 Current-Source Load for the Di
Page 179 and 180: the node (exclusive of the separate
Page 181 and 182: 14.5 Two-Stage Amplifier with Curre
Page 183 and 184: 14.6 Output Buffer Stage It is evid
Page 185 and 186: Suppose that ID6 = 400 µA, W6 = 50
Page 187 and 188: Av and Ro are calculated once, usin
Page 189 and 190: Since the source follower of M1 has
Page 191 and 192: 14.9 Summary of Equations CMRR = 1
Page 193: Unit A. Communicating with the Circ
Page 196 and 197: Place AI Acquire Waveform.vi in the
Page 200 and 201: Now go to the Diagram (under Menu W
Page 202 and 203: To complete connections to the term
Page 204 and 205: Now use the Edit Text Tool to edit
Page 206 and 207: on the left in the diagram . The Wh
Page 208 and 209: Figure A.15. Frame of Sequence Stru
Page 210 and 211: The transition regions are nonabrup
Page 212 and 213: during the oscilloscope measurement
Page 214 and 215: Unit B. Characterization of the Bip
Page 216 and 217: junction diodes, the current is lar
Page 218 and 219: common to the input and output and
Page 220 and 221: B.2 Base-Width Dependence on Juncti
Page 222 and 223: Figure B.8. Diodelike characteristi
Page 224 and 225: The minus sign comes from having as
Page 226 and 227: Figure B.10. Circuit for measuring
Page 228 and 229: B.5 Output Characteristics of BJT i
Page 230 and 231: After measuring the output characte
Page 232 and 233: B.6 SPICE Solution for IC versus VC
Page 234 and 235: B.7 Collector-Emitter Voltage and C
Page 236 and 237: B.8 DC as a Function of Collector C
Page 238 and 239: B.10 Summary of Equations Common-em
Page 240 and 241: Unit C. Common-Emitter Amplifier St
Page 242 and 243: The equation set above has three un
Page 244 and 245: The output-resistance parameter, ro
Page 246 and 247: of βDC as possible. Signal paramet
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Equation C.17 We note that the magn
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C.4 Accuracy of Transistor Gain Mea
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C.5 Effect of Finite Slope of the T
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It follows that for this case, f3dB
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C.7 Common-Emitter Amplifier with A
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Equation C.41 where IC IC(VCE), tha
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Applied voltage Vo sums up to Equat
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C.7.3 DC (Bias) of the NPN - PNP Am
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where Equation C.58 and Equation C.
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Equation C.67 The result is signifi
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The following form of the result pr
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This is equivalent to a unity-gain
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C.11 Summary of Circuit Equations B
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C.12 Exercises and Projects Project
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P1.1 Resistor Voltage-Divider Measu
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• Place AO Update Channel.vi in F
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• (Optional) To install the circu
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Procedure • Set your value of RG2
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• In the Diagram, we will add Get
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P1.4 Resistor Voltage Divider with
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• Now move the capacitor C2 = C1
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P2.1 NMOS Common-Source Circuit wit
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• In the Diagram (below), place,
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P2.2 NMOS Common-Source Amplifier w
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P2.3 Amplifier with Signal and Gain
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• Connect to FG1Chan.vi, the vari
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P3.1 SPICE Parameters and Pin Diagr
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P3.3 PMOS Transistor Use pins 6 (ga
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Procedure • Run PMOSlinear.vi and
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Procedure • Run PMOSparsub.vi wit
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Procedure • Run PMOSparam.vi to r
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Active Region Procedure • Install
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Laboratory Project 4. Characterizat
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P4.2 NMOS Transistor Use CD4007 pin
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P4.4 NMOS Parameters from the Trans
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P4.5 NMOS Lambda from the Transfer
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P4.6 NMOS Gamma SubVI Components No
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• Set RS. With NMOSgamsub.vi open
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• A file can be obtained from the
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P5.1 SPICE Equations and Pin Diagra
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P5.3 Amplifier Gain at One Bias Cur
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P5.4 Amplifier Gain versus Bias Cur
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Laboratory Project 6. PMOS Common-
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P6.2 SPICE PMOS and Circuit Equatio
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P6.4 Amplifier Gain LabVIEW Computa
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P6.5 Amplifier Frequency Response P
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P7.1 Chip Diagram and SPICE Equatio
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P7.3 Amplifier Gain at Optimum Bias
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P7.4 Optimum Bias Stability Test
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P7.5 Amplifier Frequency Response P
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Laboratory Project 8. NMOS Source-
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P8.2 Source-Follower DC Evaluation
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available for the next VI. It is us
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Laboratory Project 9. MOSFET Differ
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P9.2 DC Evaluation of the Single-Po
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P9.3 Determination of the PMOS Para
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Gains will be obtained from the gra
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• Run SweepSim.vi to obtain the d
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Laboratory Project 10. Current Mirr
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P10.2 Evaluation of the Current-Sou
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P10.4 Evaluation of the Bias Setup
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Laboratory Project 11. Operational
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P11.2 Bias Circuit Setup 1 Offset N
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P11.3 Opamp Offset Voltage Componen
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P11.4 Evaluation of the Bias Balanc
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VOH • Reset the Chan0_out Range,
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P11.6 Evaluation of the Gain with S
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P11.7 Determination of the Opamp Fr
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Laboratory Project 12. Operational
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P12.2 Opamp Integrator Components R
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Procedure • Turn off the power su
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Laboratory Project A. Communicating
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PA.2 Sending and Receiving Voltages
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Bipolar TABLE PA.2 0 to +5V 1.22 mV
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PA.5 Observing the Oscilloscope Out
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of the DAC. The steps are 2.44 mV f
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• The example here illustrates th
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Laboratory Project B. Characterizat
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PB.2 SPICE Equations SPICE Equation
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parameters nF and IS. • Connect C
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PB.4 DC versus the Collector Curren
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• Now open VI, IC_VCE.vi. Set the
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Laboratory Project C1. NPN Common-
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PC.2 DC Circuit Setup and Parameter
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PC.3 Amplifier Gain at One Bias Cur
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PC.4 Amplifier Gain versus Bias Cur
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• Run FreqResp.vi. Verify that in
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PC.6 SPICE Equations and Pin Diagra
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• Determine the value of VAF spec
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• Set the Run Mode switch to Set
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• Now reset VCC(init) and VBB(ini
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Bias Circuit

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