Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...

• Since there might not be any Verilog statement that can
model the analog block, the analog block contains only I/O
port information.
• Must be enabled Don’t Touch when synthesis.
– Using Attributes Optimization Directives Design
module A_module_1(J, T, Y) ;
input [7:0] J, T ;
output Y;
endmodule
Module Declaration
module core_top(clk, In, Y)
input clk ;
input [5:0] In ;
Output Y ;
latcha La1 ( clk, In, J ) ;
A_module_1 IM1 ( J, T, Y) ;
endmodule
120 Mixed-Signal IC Design Kit