Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...

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Place Analog Block • Select the block and move it to the desired location. • Place blocks with Optimize routablility by setting Span On. • Place blocks along the edges of core area, preferably in a corner of the core. • Use Floorplans Update Core Rows after all blocks placed. • Set Global Block Hale in Update Core Rows windows to reserve spacing for block power ring. 136 Mixed-Signal IC Design Kit
Plan Power • Use Route Plan Power, delete power path that analog block does not routed. • Modify the following variables in PP Add Rings form. – Nets name: “VDD VSS” – Ring Layer: METAL3 for Horizontal METAL2 for Vertical – Core Ring Width the same as Block Ring Width • Modify the variables in PP Add Stripes form, if you need. 137 Mixed-Signal IC Design Kit
Page 2 and 3:
Day 1 Introduction of Mixed-Signal
Page 4 and 5:
SoC IP Based Design CORE Zone 4: Gl
Page 7 and 8:
Sensor Analog chip Sensor Integrati
Page 9 and 10:
Challenge of Integration • High d
Page 11 and 12:
Conventional Design Concept for Blo
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Digital Model Abstraction Digital m
Page 16 and 17:
Enabling the Top-Down Design • Be
Page 18 and 19:
Top-Down Design Methodology Top-Dow
Page 20 and 21:
What Can’t Be Expected with Mixed
Page 22 and 23:
Digital Abstraction Mixed-Signal Si
Page 24 and 25:
Basics of Mixed Signal Simulation
Page 26 and 27:
Core Modification Glued Mixed-Signa
Page 29 and 30:
The Cadence environment can be invo
Page 31 and 32:
Verimix Mixed-Signal Tool Environme
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Before the Design Creation • Syst
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Device / Analog leaf cell The block
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Partition Requirement • The desig
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Interface Elements • Generated au
Page 41 and 42:
Analog Modeling for Mixed Signal De
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Analog Hardware Description Languag
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Disciplines Electrical magnetic the
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Analog Modeling Issues • The Anal
Page 49 and 50:
MS HDL Simulation Flow 49 Mixed-Sig
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Creating the HDL View of Designed B
Page 53 and 54:
Creating Analog Block and Symbol Cr
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Integrating the whole design within
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Schematics in Verilog-A Modules 57
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Modelwrtier: the utility for creati
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Digital Stimuli Analog Stimuli Addi
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1. Create a behavioral view for the
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Create Config View for Simulation T
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After Setting Configuration The Hie
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The default value can be preset in
Page 73 and 74:
Change View Selection With Hierarch
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Specify Simulation Environment Use
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Choosing Simulator/Directory/Host T
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Level 1 Digital to Analog Interface
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Level 3 Digital to Analog interface
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Modification of IE Parameters • T
Page 87 and 88: Some of the parameter values might
Page 89 and 90: Define the signals to plotted after
Page 91 and 92: module CCADCtop; supply1 N2; supply
Page 93 and 94: Simulation Options for Digital Simu
Page 95 and 96: Run Log Files Message for digital s
Page 97 and 98: • After Simulation, the selected
Page 99 and 100: Invoke by Tool Parametric Analysis
Page 101 and 102: Feature of HDL debug • Set breakp
Page 103 and 104: Analog blocks Digital domain Layout
Page 105 and 106: • Definition: Prepare Data for SE
Page 107 and 108: Cadence Abstract Generator • Cade
Page 109 and 110: Entering Technology Information •
Page 111 and 112: • After you specify technology in
Page 113 and 114: • Pins: - The Abstract Generator
Page 115 and 116: • Verify: Verify - During the ver
Page 117 and 118: • LEF file • Verilog file • C
Page 119 and 120: Verilog File of TSMC .35um 2P4M •
Page 122 and 123: • LEF file • Verilog file • C
Page 124 and 125: environment.gcf GCF File (gcf (head
Page 126 and 127: … Header( Library("IMatrix8x8") D
Page 128 and 129: CTLF File of TSMC .35um 2P4M • Di
Page 130 and 131: Place IO Constraints Create placeIO
Page 132 and 133: Import LEF File • Before creating
Page 134 and 135: Import Verilog File • CIC provide
Page 138 and 139: Add PRDIODE • To support a separa
Page 140 and 141: Placement • Place -> Cells • Qp
Page 142 and 143: Use Ultra Router • The ultra rout
Page 144 and 145: Prepare for Layout Verification •
Page 146 and 147: Modify Layout • As the layout of
Page 148 and 149: Calibre DRC Flow • Edit the Calib
Page 150 and 151: Calibre LVS Flow (Cont.) • Add an
Page 152 and 153: Mixed Signal Parasitic Simulation
Page 154 and 155: Transistor Level Post-Layout Simula
Page 156 and 157: Timemill Input Stimulus File • Cr
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