Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...
Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...
Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...
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A module represents the fundamental user-defined primitive in Verilog-A<br />
Include natures,<br />
discipline & constants<br />
Interface Declarations<br />
name, ports and<br />
parameters<br />
Global Module Scope<br />
local variables and<br />
analog block<br />
Basic Module Definition<br />
Behavioral<br />
Description<br />
`include “constants.h”<br />
`include “discipline.h”<br />
module res1(p, n) ;<br />
inout p, n ;<br />
electrical p, n;<br />
parameter real r=1 from ( 0:inf) ;<br />
parameter real tc=1.5m from [0:3m) ;<br />
real reff;<br />
analog begin<br />
@(initial_step(“static”)) begin<br />
reff = r*(1+tc*$temperature) ;<br />
end<br />
I(p,n)