Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...
Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...
Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...
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Created Netlist(Analog)<br />
HNL : Hierarchical Netlist<br />
FNL : Flat netlist - for parasitic analysis, detailed IE mode<br />
simulator lang= spectre<br />
vi0 (5 0) vsource type= pulse val0=-5.00000000E-01 val1=0.0 period=10.0<br />
+delay=5e-9 rise=500e-12 fall=500e-12 width=1.0<br />
vi1 (12 0) vsource type= pulse val0=-5.00000000E-01 val1=0.0<br />
+period=+1.50000000E-08 delay=1e-9 rise=500e-12 fall=500e-12<br />
+width=+5.00000000E-09<br />
qi2 (25 39 2) tp1 region= fwd area=1 m=1.0<br />
simulator lang= spice<br />
* BEGIN Interface Element Header<br />
da99978 99978 0 d2a src="99978" val0=500.0m val1=4.5 rise=1n fall=1n ron=1<br />
R99978 99978 10 10<br />
da99979 99979 0 d2a src="99979" val0=500.0m val1=4.5 rise=1n fall=1n ron=1<br />
R99979 99979 14 10<br />
da99980 99980 0 d2a src="99980" val0=500.0m val1=4.5 rise=1n fall=1n ron=1<br />
R99980 99980 30 10<br />
da99981 99981 0 d2a src="99981" val0=500.0m val1=4.5 rise=1n fall=1n ron=1<br />
90 <strong>Mixed</strong>-<strong>Signal</strong> <strong>IC</strong> <strong>Design</strong> <strong>Kit</strong>