Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...

More documents

Recommendations

Info

Design Partitioning Scheme • The partitioning scheme in Affirma Analog Artist is Instance-based • Partition is defined before netlisting, each leaf cell must be separated into either digital or analog netlist • The default partition scheme is based on stop view values Analog Stop View Set : spectreS cdsSpice spice ahdl auLvs spectre veriloga Digital Stop View Set : behavioral functional hdl system verilogNetlist verilog vhdlImport • The schematic partition can be displayed/defined within schematic window 36 Mixed-Signal IC Design Kit
Partition Requirement • The design must contain at least one analog component. • The design must contain at least one digital component. • There must be with at least one interface net. • Analog stimuli defined in the analog stimuli file cannot be used to drive digital net. • Digital stimuli defined in the digital stimuli file can not be used to drive analog net. • Any interface net must be identified before netlisting. 37 Mixed-Signal IC Design Kit
Page 2 and 3: Day 1 Introduction of Mixed-Signal
Page 4 and 5: SoC IP Based Design CORE Zone 4: Gl
Page 7 and 8: Sensor Analog chip Sensor Integrati
Page 9 and 10: Challenge of Integration • High d
Page 11 and 12: Conventional Design Concept for Blo
Page 13: Digital Model Abstraction Digital m
Page 16 and 17: Enabling the Top-Down Design • Be
Page 18 and 19: Top-Down Design Methodology Top-Dow
Page 20 and 21: What Can’t Be Expected with Mixed
Page 22 and 23: Digital Abstraction Mixed-Signal Si
Page 24 and 25: Basics of Mixed Signal Simulation
Page 26 and 27: Core Modification Glued Mixed-Signa
Page 29 and 30: The Cadence environment can be invo
Page 31 and 32: Verimix Mixed-Signal Tool Environme
Page 33 and 34: Before the Design Creation • Syst
Page 35: Device / Analog leaf cell The block
Page 39 and 40: Interface Elements • Generated au
Page 41 and 42: Analog Modeling for Mixed Signal De
Page 43 and 44: Analog Hardware Description Languag
Page 45 and 46: Disciplines Electrical magnetic the
Page 47 and 48: Analog Modeling Issues • The Anal
Page 49 and 50: MS HDL Simulation Flow 49 Mixed-Sig
Page 51 and 52: Creating the HDL View of Designed B
Page 53 and 54: Creating Analog Block and Symbol Cr
Page 55 and 56: Integrating the whole design within
Page 57 and 58: Schematics in Verilog-A Modules 57
Page 59 and 60: Modelwrtier: the utility for creati
Page 61 and 62: Digital Stimuli Analog Stimuli Addi
Page 63 and 64: 1. Create a behavioral view for the
Page 65 and 66: Create Config View for Simulation T
Page 67: After Setting Configuration The Hie
Page 70: The default value can be preset in
Page 73 and 74: Change View Selection With Hierarch
Page 76 and 77: Specify Simulation Environment Use
Page 78 and 79: Choosing Simulator/Directory/Host T
Page 80 and 81: Level 1 Digital to Analog Interface
Page 82 and 83: Level 3 Digital to Analog interface
Page 84 and 85: Modification of IE Parameters • T
Page 87 and 88:
Some of the parameter values might
Page 89 and 90:
Define the signals to plotted after
Page 91 and 92:
module CCADCtop; supply1 N2; supply
Page 93 and 94:
Simulation Options for Digital Simu
Page 95 and 96:
Run Log Files Message for digital s
Page 97 and 98:
• After Simulation, the selected
Page 99 and 100:
Invoke by Tool Parametric Analysis
Page 101 and 102:
Feature of HDL debug • Set breakp
Page 103 and 104:
Analog blocks Digital domain Layout
Page 105 and 106:
• Definition: Prepare Data for SE
Page 107 and 108:
Cadence Abstract Generator • Cade
Page 109 and 110:
Entering Technology Information •
Page 111 and 112:
• After you specify technology in
Page 113 and 114:
• Pins: - The Abstract Generator
Page 115 and 116:
• Verify: Verify - During the ver
Page 117 and 118:
• LEF file • Verilog file • C
Page 119 and 120:
Verilog File of TSMC .35um 2P4M •
Page 122 and 123:
• LEF file • Verilog file • C
Page 124 and 125:
environment.gcf GCF File (gcf (head
Page 126 and 127:
… Header( Library("IMatrix8x8") D
Page 128 and 129:
CTLF File of TSMC .35um 2P4M • Di
Page 130 and 131:
Place IO Constraints Create placeIO
Page 132 and 133:
Import LEF File • Before creating
Page 134 and 135:
Import Verilog File • CIC provide
Page 136 and 137:
Place Analog Block • Select the b
Page 138 and 139:
Add PRDIODE • To support a separa
Page 140 and 141:
Placement • Place -> Cells • Qp
Page 142 and 143:
Use Ultra Router • The ultra rout
Page 144 and 145:
Prepare for Layout Verification •
Page 146 and 147:
Modify Layout • As the layout of
Page 148 and 149:
Calibre DRC Flow • Edit the Calib
Page 150 and 151:
Calibre LVS Flow (Cont.) • Add an
Page 152 and 153:
Mixed Signal Parasitic Simulation
Page 154 and 155:
Transistor Level Post-Layout Simula
Page 156 and 157:
Timemill Input Stimulus File • Cr
show all

Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...

Create successful ePaper yourself

Delete template?

Save as template?