Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...

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• Push the limit of system performance Reduce parasitic Reduce I/O driving loads Exploit design space between blocks • Push the limit of power dissipation Reduce parasitic loads Reduce I/O driving currents • Reduce the system size Benefit of Integration 8 Mixed-Signal IC Design Kit
Challenge of Integration • High design complexity Capacity and Efficiency of EDA tool Different design knowledge • Increasing process complexity • Signal coupling prevention Signals getting closer Signals might be virtually connected • Signal noise isolation Isolation between noisy circuit and sensitive circuit 9 Mixed-Signal IC Design Kit
Page 2 and 3: Day 1 Introduction of Mixed-Signal
Page 4 and 5: SoC IP Based Design CORE Zone 4: Gl
Page 7: Sensor Analog chip Sensor Integrati
Page 11 and 12: Conventional Design Concept for Blo
Page 13: Digital Model Abstraction Digital m
Page 16 and 17: Enabling the Top-Down Design • Be
Page 18 and 19: Top-Down Design Methodology Top-Dow
Page 20 and 21: What Can’t Be Expected with Mixed
Page 22 and 23: Digital Abstraction Mixed-Signal Si
Page 24 and 25: Basics of Mixed Signal Simulation
Page 26 and 27: Core Modification Glued Mixed-Signa
Page 29 and 30: The Cadence environment can be invo
Page 31 and 32: Verimix Mixed-Signal Tool Environme
Page 33 and 34: Before the Design Creation • Syst
Page 35 and 36: Device / Analog leaf cell The block
Page 37 and 38: Partition Requirement • The desig
Page 39 and 40: Interface Elements • Generated au
Page 41 and 42: Analog Modeling for Mixed Signal De
Page 43 and 44: Analog Hardware Description Languag
Page 45 and 46: Disciplines Electrical magnetic the
Page 47 and 48: Analog Modeling Issues • The Anal
Page 49 and 50: MS HDL Simulation Flow 49 Mixed-Sig
Page 51 and 52: Creating the HDL View of Designed B
Page 53 and 54: Creating Analog Block and Symbol Cr
Page 55 and 56: Integrating the whole design within
Page 57 and 58: Schematics in Verilog-A Modules 57
Page 59 and 60:
Modelwrtier: the utility for creati
Page 61 and 62:
Digital Stimuli Analog Stimuli Addi
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1. Create a behavioral view for the
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Create Config View for Simulation T
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After Setting Configuration The Hie
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The default value can be preset in
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Change View Selection With Hierarch
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Specify Simulation Environment Use
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Choosing Simulator/Directory/Host T
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Level 1 Digital to Analog Interface
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Level 3 Digital to Analog interface
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Modification of IE Parameters • T
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Some of the parameter values might
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Define the signals to plotted after
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module CCADCtop; supply1 N2; supply
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Simulation Options for Digital Simu
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Run Log Files Message for digital s
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• After Simulation, the selected
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Invoke by Tool Parametric Analysis
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Feature of HDL debug • Set breakp
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Analog blocks Digital domain Layout
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• Definition: Prepare Data for SE
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Cadence Abstract Generator • Cade
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Entering Technology Information •
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• After you specify technology in
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• Pins: - The Abstract Generator
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• Verify: Verify - During the ver
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• LEF file • Verilog file • C
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Verilog File of TSMC .35um 2P4M •
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• LEF file • Verilog file • C
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environment.gcf GCF File (gcf (head
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… Header( Library("IMatrix8x8") D
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CTLF File of TSMC .35um 2P4M • Di
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Place IO Constraints Create placeIO
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Import LEF File • Before creating
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Import Verilog File • CIC provide
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Place Analog Block • Select the b
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Add PRDIODE • To support a separa
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Placement • Place -> Cells • Qp
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Use Ultra Router • The ultra rout
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Prepare for Layout Verification •
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Modify Layout • As the layout of
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Calibre DRC Flow • Edit the Calib
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Calibre LVS Flow (Cont.) • Add an
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Mixed Signal Parasitic Simulation
Page 154 and 155:
Transistor Level Post-Layout Simula
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Timemill Input Stimulus File • Cr
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