Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...

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Created Netlist(Analog) HNL : Hierarchical Netlist FNL : Flat netlist - for parasitic analysis, detailed IE mode simulator lang= spectre vi0 (5 0) vsource type= pulse val0=-5.00000000E-01 val1=0.0 period=10.0 +delay=5e-9 rise=500e-12 fall=500e-12 width=1.0 vi1 (12 0) vsource type= pulse val0=-5.00000000E-01 val1=0.0 +period=+1.50000000E-08 delay=1e-9 rise=500e-12 fall=500e-12 +width=+5.00000000E-09 qi2 (25 39 2) tp1 region= fwd area=1 m=1.0 simulator lang= spice * BEGIN Interface Element Header da99978 99978 0 d2a src="99978" val0=500.0m val1=4.5 rise=1n fall=1n ron=1 R99978 99978 10 10 da99979 99979 0 d2a src="99979" val0=500.0m val1=4.5 rise=1n fall=1n ron=1 R99979 99979 14 10 da99980 99980 0 d2a src="99980" val0=500.0m val1=4.5 rise=1n fall=1n ron=1 R99980 99980 30 10 da99981 99981 0 d2a src="99981" val0=500.0m val1=4.5 rise=1n fall=1n ron=1 90 Mixed-Signal IC Design Kit
module CCADCtop; supply1 N2; supply0 N1; supply0 N0; // registers for ie elements reg N12; // /net92 reg N7; // /comOut reg N99995; // /net96 reg N99996; // /net79 reg N6; // /net53 reg N17; // /net96 reg N5; // /net79 specify specparam CDS_LIBNAME = "ccadcLib"; specparam CDS_CELLNAME = "CCADCtop"; specparam CDS_VIEWNAME = "schematic"; endspecify buf I3( N8, N19 ); buf I4( N15, N28 ); Created Netlist(Digital) // Begin Interface Element Header and Verimix //Synchronization task initial begin $vmx_initialize( "spectre", dc_mode_flag); $vmx_define_export( N10, "99978"); // /net70 $vmx_define_import( N12, "99986"); // /net92 $vmx_define_import( N7, "99987"); // /comOut $vmx_define_import( N99988, “99988”); // /net53 end // End Interface Element Footer and Verimix // Synchronization task // Begin WSF Save Waveforms initial begin $save_waveform( "binary" ,"/net86", test.top.N4 ,"/Q2", test.top.N23 ); end // End WSF Save Waveforms endmodule 91 Mixed-Signal IC Design Kit
Page 2 and 3:
Day 1 Introduction of Mixed-Signal
Page 4 and 5:
SoC IP Based Design CORE Zone 4: Gl
Page 7 and 8:
Sensor Analog chip Sensor Integrati
Page 9 and 10:
Challenge of Integration • High d
Page 11 and 12:
Conventional Design Concept for Blo
Page 13:
Digital Model Abstraction Digital m
Page 16 and 17:
Enabling the Top-Down Design • Be
Page 18 and 19:
Top-Down Design Methodology Top-Dow
Page 20 and 21:
What Can’t Be Expected with Mixed
Page 22 and 23:
Digital Abstraction Mixed-Signal Si
Page 24 and 25:
Basics of Mixed Signal Simulation
Page 26 and 27:
Core Modification Glued Mixed-Signa
Page 29 and 30:
The Cadence environment can be invo
Page 31 and 32:
Verimix Mixed-Signal Tool Environme
Page 33 and 34:
Before the Design Creation • Syst
Page 35 and 36:
Device / Analog leaf cell The block
Page 37 and 38:
Partition Requirement • The desig
Page 39 and 40: Interface Elements • Generated au
Page 41 and 42: Analog Modeling for Mixed Signal De
Page 43 and 44: Analog Hardware Description Languag
Page 45 and 46: Disciplines Electrical magnetic the
Page 47 and 48: Analog Modeling Issues • The Anal
Page 49 and 50: MS HDL Simulation Flow 49 Mixed-Sig
Page 51 and 52: Creating the HDL View of Designed B
Page 53 and 54: Creating Analog Block and Symbol Cr
Page 55 and 56: Integrating the whole design within
Page 57 and 58: Schematics in Verilog-A Modules 57
Page 59 and 60: Modelwrtier: the utility for creati
Page 61 and 62: Digital Stimuli Analog Stimuli Addi
Page 63 and 64: 1. Create a behavioral view for the
Page 65 and 66: Create Config View for Simulation T
Page 67: After Setting Configuration The Hie
Page 70: The default value can be preset in
Page 73 and 74: Change View Selection With Hierarch
Page 76 and 77: Specify Simulation Environment Use
Page 78 and 79: Choosing Simulator/Directory/Host T
Page 80 and 81: Level 1 Digital to Analog Interface
Page 82 and 83: Level 3 Digital to Analog interface
Page 84 and 85: Modification of IE Parameters • T
Page 87 and 88: Some of the parameter values might
Page 89: Define the signals to plotted after
Page 93 and 94: Simulation Options for Digital Simu
Page 95 and 96: Run Log Files Message for digital s
Page 97 and 98: • After Simulation, the selected
Page 99 and 100: Invoke by Tool Parametric Analysis
Page 101 and 102: Feature of HDL debug • Set breakp
Page 103 and 104: Analog blocks Digital domain Layout
Page 105 and 106: • Definition: Prepare Data for SE
Page 107 and 108: Cadence Abstract Generator • Cade
Page 109 and 110: Entering Technology Information •
Page 111 and 112: • After you specify technology in
Page 113 and 114: • Pins: - The Abstract Generator
Page 115 and 116: • Verify: Verify - During the ver
Page 117 and 118: • LEF file • Verilog file • C
Page 119 and 120: Verilog File of TSMC .35um 2P4M •
Page 122 and 123: • LEF file • Verilog file • C
Page 124 and 125: environment.gcf GCF File (gcf (head
Page 126 and 127: … Header( Library("IMatrix8x8") D
Page 128 and 129: CTLF File of TSMC .35um 2P4M • Di
Page 130 and 131: Place IO Constraints Create placeIO
Page 132 and 133: Import LEF File • Before creating
Page 134 and 135: Import Verilog File • CIC provide
Page 136 and 137: Place Analog Block • Select the b
Page 138 and 139: Add PRDIODE • To support a separa
Page 140 and 141:
Placement • Place -> Cells • Qp
Page 142 and 143:
Use Ultra Router • The ultra rout
Page 144 and 145:
Prepare for Layout Verification •
Page 146 and 147:
Modify Layout • As the layout of
Page 148 and 149:
Calibre DRC Flow • Edit the Calib
Page 150 and 151:
Calibre LVS Flow (Cont.) • Add an
Page 152 and 153:
Mixed Signal Parasitic Simulation
Page 154 and 155:
Transistor Level Post-Layout Simula
Page 156 and 157:
Timemill Input Stimulus File • Cr
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