Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...

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Set Instance Binding With menu Hierarchy-Editor Set Instance Binding… , the following form will be shown for redefining the cell view to use for a certain instance. Select a instance and choose the view to bin binded 69 Mixed-Signal IC Design Kit
Page 2 and 3:
Day 1 Introduction of Mixed-Signal
Page 4 and 5:
SoC IP Based Design CORE Zone 4: Gl
Page 7 and 8:
Sensor Analog chip Sensor Integrati
Page 9 and 10:
Challenge of Integration • High d
Page 11 and 12:
Conventional Design Concept for Blo
Page 13:
Digital Model Abstraction Digital m
Page 16 and 17:
Enabling the Top-Down Design • Be
Page 18 and 19: Top-Down Design Methodology Top-Dow
Page 20 and 21: What Can’t Be Expected with Mixed
Page 22 and 23: Digital Abstraction Mixed-Signal Si
Page 24 and 25: Basics of Mixed Signal Simulation
Page 26 and 27: Core Modification Glued Mixed-Signa
Page 29 and 30: The Cadence environment can be invo
Page 31 and 32: Verimix Mixed-Signal Tool Environme
Page 33 and 34: Before the Design Creation • Syst
Page 35 and 36: Device / Analog leaf cell The block
Page 37 and 38: Partition Requirement • The desig
Page 39 and 40: Interface Elements • Generated au
Page 41 and 42: Analog Modeling for Mixed Signal De
Page 43 and 44: Analog Hardware Description Languag
Page 45 and 46: Disciplines Electrical magnetic the
Page 47 and 48: Analog Modeling Issues • The Anal
Page 49 and 50: MS HDL Simulation Flow 49 Mixed-Sig
Page 51 and 52: Creating the HDL View of Designed B
Page 53 and 54: Creating Analog Block and Symbol Cr
Page 55 and 56: Integrating the whole design within
Page 57 and 58: Schematics in Verilog-A Modules 57
Page 59 and 60: Modelwrtier: the utility for creati
Page 61 and 62: Digital Stimuli Analog Stimuli Addi
Page 63 and 64: 1. Create a behavioral view for the
Page 65 and 66: Create Config View for Simulation T
Page 67: After Setting Configuration The Hie
Page 72 and 73: Define Detailed Interface Elements
Page 74: Configuration of HE Display The con
Page 77 and 78: With Setup window to define simulat
Page 79 and 80: Interface Element Model Definition
Page 81 and 82: Level 2 Digital to Analog Interface
Page 83 and 84: MOS1_a2d Analog to Digital Interfac
Page 85: Device Model Specification The acti
Page 88 and 89: Define the analysis type through th
Page 90 and 91: Created Netlist(Analog) HNL : Hiera
Page 92 and 93: Simulation Options for Analog Simul
Page 94 and 95: Submit the Simulation Execute the s
Page 96 and 97: Result Browser After several simula
Page 98 and 99: Waveform Calculator If further calc
Page 100 and 101: For the HDL design, the Verilog-A i
Page 102 and 103: Layout Integration and Verification
Page 104 and 105: • LEF file • Verilog file • C
Page 106 and 107: LEF File of TSMC .35um 2P4M • Dig
Page 108 and 109: Cadence Abstract Generator Flow Ent
Page 110 and 111: Opening a Library • Included in t
Page 112 and 113: Distributing Cells • Central to t
Page 114 and 115: • Abstract: Generating Abstracts
Page 116 and 117: Exporting • If you are using Sili
Page 118 and 119:
Prepare Data for SE : Verilog File
Page 120:
• Since there might not be any Ve
Page 123 and 124:
• Definition: Prepare Data for SE
Page 125 and 126:
(HEADER… ) (GLOBAL … (Subset Ti
Page 127 and 128:
Compiled TLF File • SE only reads
Page 129 and 130:
Layout Integration • After prepar
Page 131 and 132:
SE Startup • Before start SE, cre
Page 133 and 134:
Import Timing Library • After APR
Page 135 and 136:
Initiate Floorplan • Set the two
Page 137 and 138:
Plan Power • Use Route Plan Powe
Page 139 and 140:
Add IO Filler • Connect io pad po
Page 141 and 142:
• Stripe Connect Rings - Connect
Page 143 and 144:
Verification for Mixed-Signal Desig
Page 145 and 146:
Read into DFII Library • After ex
Page 147 and 148:
Export Layout • In Virtuoso, dele
Page 149 and 150:
Calibre LVS Flow • Using “v2lvs
Page 151 and 152:
Post-Layout Simulation for Mixed-Si
Page 153 and 154:
Flows for Parasitic Simulation •
Page 155 and 156:
Prepare layout Replace Layout View
Page 157:
Reference • Mixed-Mode Simulation
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Mixed-Signal IC Design Kit Training Manual - Electrical & Computer ...

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