PhD Thesis Arne Lüker final version V4 - Cranfield University

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142 PST as a buffer layer for PZT on SiO2 PST as a buffer layer for PZT on SiO2 As mentioned previously the most common and probably studied ferroelectric thin film prepared via sol-gel today is PZT. A huge number of devices and applications, like FBARs for mobile phones, infrared detectors, sonar transducers for military but also for medical reasons and so on, have been realised with this material. As MEMS applications are concerned, a thin and flexible structural layer is employed with PZT films deposited onto it and followed by further processing to realise on-chip sensing and actuation depending on specific device design. The most commonly used structural material is an Fig. 8.1: Cracks in a PZT thin film on SiO2/Si active Si layer on SOI (silicon-on-insulator) wafers. Another choice is silicon nitride, Si3N4 (SiNx) layer, as it can be prepared with low stress on standard Si substrates and is used as membranes in MEMS devices or LIGA applications. SiNx as a structural layer could also provide better tunablity of stress-induced pre- bending of PZT cantilever in a well-designed device structure. Ideally the PZT device structures consist of PZT thin films sandwiched between two electrodes and usually integrated onto a Si substrate, typically resembling a planar capacitor layer design (see Appendix A). The quality of PZT thin films and its fatigue behaviour depend on various factors such as thermal compatibility of the compositional layers, their interfaces, the microstructures, crystal defects and oxygen vacancies, thereby influencing the performance and reliability of the <strong>final</strong> PZT microdevices in MEMS applications [1, 2]. A key concern in integrating ferroelectric films is the suppression of interdiffusion of the constituent elements and compositional fluctuation in multi-layer stacks forming the microdevices. It is now established that thermal stability of the electrodes is crucial for high quality growth of PZT thin film, and platinum (Pt) is widely used as a bottom electrode because of its stability and good lattice match to PZT films. In addition, Pt also provides the fleeting formation of a favourable intermetallic phase, namely Pt3Pb,
Sol-Gel derived Ferroelectric Thin Films for Voltage Tunable Applications promoting nucleation and the formation of preferred PZT (111) perovskite grains during crystallisation of PZT films on its top [3, 4]. However, a suitable diffusion barrier layer must be inserted between the bottom Pt electrode and Si substrate to limit the diffusion of lead (Pb) during PZT crystallisation at elevated temperature in an oxidising atmosphere, thereby preventing microcracks and delamination caused by Pt hillock formation [5], see Fig. 8.1 and 8.2. The buffer layer plays a significant role in improving interfaces in PZT device structures and provides better adhesion between the substrate and PZT device layers that should ensure favourable PZT microstructures development with dense and homogeneous grain distribution [6]. It is evident that the buffer layer can influence the crystalline phase nucleation of the PZT by altering the activation energy and the nucleation temperature in PZT transducer stacks. The structural evaluation of the diffusion barrier is, therefore, necessary to optimise the PZT transducer design and enhance the piezoelectric performance of the PZT microdevices. Until recently most research studies have been considered with incorporating various oxides and intermetallic materials as the diffusion barrier layer to obtain crack-free PZT thin film on a Si and SiNx structural layer. Barrier layers studied extensively include TiO2, ZrO2, Al2O3, Ti-Al, Ir(Pt)/TiN and LaNiO3, produced using a wide range of deposition techniques [4, 6, 7]. Fig. 8.2: Pt hillock formation due to high temperatures. The results of the last chapter are encouraging enough to study PST as a buffer layer between PZT and SiO2. PST has a similar perovskite-type crystal structure and a lattice mismatch of only ~3% to PZT thin films [8] and it was shown here that PST crystallises crack-free into the perovskite crystal structure on SiO2. In integrating PZT microdevices at wafer-scale, it is often desirable to deposit PZT thin films on non-uniform surface by modifying the process layout that allows patterning of the bottom Pt/Ti electrode as the first step, prior to spin-coating of PZT. This is important because patterning of the PZT transducer stacks by plasma etching from the top electrode to bottom substrate 143
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Sol-Gel derived Ferroelectric Thin
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Abstract Ferroelectric perovskite t
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Table of Content Introduction and M
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Page 93 and 94: Sol-Gel derived Ferroelectric Thin
Page 99 and 100: Intensity [arb. Units] (g) (f) (e)
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Page 113 and 114: Intensity [arb. Units] Intensity [a
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Page 131 and 132: (g) (f) (e) (d) (c) (b) (a) Sol-Gel
Page 143: Sol-Gel derived Ferroelectric Thin
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PhD Thesis Arne Lüker final version V4 - Cranfield University

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