Xeon-Phi-Coprocessor-Datasheet

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Table 4-2. 5120D (DFF) SKU Pinout B80 GND A80 PERp15 I B81 PRSNT2_N I A81 PERn15 I B82 RSVD NC A82 GND B83 RSVD NC A83 RSVD NC B84 RSVD NC A84 RSVD NC B85 RSVD NC A85 GND B86 RSVD NC A86 RSVD NC B87 RSVD NC A87 RSVD NC B88 +12V A88 GND B89 +12V A89 GND B90 +12V A90 GND B91 +12V A91 GND B92 +12V A92 GND B93 +12V A93 GND B94 +12V A94 GND B95 +12V A95 GND B96 +12V A96 GND B97 +12V A97 GND B98 +12V A98 GND B99 +12V A99 GND B100 +12V A100 GND B101 +12V A101 GND B102 +12V A102 GND B103 +12V A103 GND B104 +12V A104 GND B105 +12V A105 GND B106 +12V A106 GND B107 +12V A107 GND B108 +12V A108 GND B109 +12V A109 GND B110 +12V A110 GND B111 +12V A111 GND B112 +12V A112 GND B113 +12V A113 GND B114 +12V A114 GND B115 +12V A115 GND Note: The 5120D SKU does not use the +3.3V_AUX power pins, and baseboard designers have the option to either route these pins or leave them unconnected. The PROCHOT_N pin on the 5120D SKU follows the definition and routing requirements listed in Section 4.1.1 Intel ® Xeon Phi Coprocessor Datasheet 50 Document ID Number: 328209 003EN
4.3.1 Baseboard Requirements of 5120D Unlike the Intel ® Xeon Phi coprocessor PCI Express* card, the 5120D SKU requires the baseboard to implement input filter for the 12V and 3.3V power rails. There are no auxiliary or external power connectors on the 5120D and all power is supplied via the 230 pin edge connector. • Each 5120D product in the system requires a dedicated input filter for the +12V rail. • The filtering circuitry should be placed as close to the connector pins as possible. • The +3.3V power rail input must meet the PCI Express* CEM specification. Table 4-3. 51xxD Power Rail Requirements on Baseboard Requirement Value +12V Min V IN 11.04V Max current 22.192A LC filter Maximum rated ripple current per capacitor considering 70% of derating= 2.254A Maximum input current slew rate at input inductor= 0.5A/us Maximum operating temperature for the input capacitors= 105°C. A typical implementation of the input filter would use 5 x 150uF (Sanyo, 16SVPC150M) capacitors and 1 x 0.2uH (Pulse, PG0426.201NL) inductor. +3.3V Decoupling caps 100µf Max Current 3A 4.3.2 AC Coupling on 5120D Data Pins Each pin on the PETp/n[15:0] and PERp/n[15:0] buses requires a 0.1µF 0402 AC coupling capacitor on the baseboard. The capacitors should be located for differential pair traces at the same location along the differential traces (that is, they should not be staggered from one trace to the other), and should be as close to each other as possible. Document ID Number: 328209 003EN Intel ® Xeon Phi Coprocessor Datasheet 51
Page 1 and 2: Intel ® Xeon Phi Coprocessor Datas
Page 3 and 4: Table of Contents 1 Introduction...
Page 5 and 6: List of Tables 1-1 Related Document
Page 7 and 8: 1 Introduction 1.1 Reference Docume
Page 9 and 10: 2 Intel ® Xeon Phi Coprocessor Arc
Page 11 and 12: Figure 2-2. Intel® Xeon Phi Coproc
Page 13 and 14: 2.1.4 Intel® Xeon Phi Coprocessor
Page 15 and 16: 3 Thermal and Mechanical Specificat
Page 17 and 18: Figure 3-2 Dimensions of the Intel
Page 19 and 20: Within 50ns of detecting T throttle
Page 21 and 22: 3.3.2 7120P/SE10P/5110P/3120P/31S1P
Page 23 and 24: Figure 3-6 Airflow Requirement vs.
Page 25 and 26: Figure 3-8 Airflow Requirement vs.
Page 27 and 28: Figure 3-10 SE10X/7120X Power Profi
Page 29 and 30: Figure 3-12 5120D Power Profile: Me
Page 31 and 32: Figure 3-14 7120D Power Profile: Me
Page 33 and 34: 3.4.2 Thermal Profile and Cooling T
Page 35 and 36: 3.4.3 Mechanical Considerations •
Page 37 and 38: Figure 3-19 SE10X/7120X Board Botto
Page 39 and 40: Figure 3-21 7120D/5120D Board Botto
Page 41 and 42: 3.5.1 Bracket Installation Steps Fi
Page 43 and 44: 3. Install OEM Bracket. a. Insert t
Page 45 and 46: 4 Intel ® Xeon Phi Coprocessor Pin
Page 47 and 48: 4.2 Supplemental Power Connector(s)
Page 49: Table 4-2. 5120D (DFF) SKU Pinout B
Page 53 and 54: 5 Power Specification and Managemen
Page 55 and 56: Figure 5-2. Some cores are in C0-st
Page 57 and 58: Figure 5-6. Package-C6 and Memory M
Page 59 and 60: Figure 5-8. Intel ® Xeon Phi copro
Page 61 and 62: 6 Manageability 6.1 Intel ® Xeon P
Page 63 and 64: — P-state clamping if the P-state
Page 65 and 66: The sensors available from the SMC
Page 67 and 68: The SMC supports a read only IPMI S
Page 69 and 70: 6.6.2.4 Read Description Figure 6-2
Page 71 and 72: 6.6.3.6 General Commands Table 6-7.
Page 73 and 74: Table 6-12. Set SM Signal Request F
Page 75 and 76: When the baseboard asserts PROCHOT
Page 77 and 78: Table 6-25. Table of Sensors Sensor

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