Xeon-Phi-Coprocessor-Datasheet
Xeon-Phi-Coprocessor-Datasheet
Xeon-Phi-Coprocessor-Datasheet
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Figure 5-4.<br />
All Cores In Package-C3 State; Memory In M1<br />
M1 M1 M1 M1 M1 M1<br />
VR<br />
Package C3 - Sleep<br />
(all core clocks<br />
gated)<br />
Fan<br />
~20%<br />
M1 M1 M1 M1 M1 M1<br />
VR<br />
Full bandwidth enabled<br />
When all cores have entered C1 Halt state, the coprocessor package can reduce the<br />
core voltage and enter Deep-pC3. The fan (on active SKUs) can slow to minimum<br />
speed. VRs enter low power mode.<br />
Figure 5-5.<br />
Package-C3 and Memory M2 state<br />
M2 M2 M2 M2 M2 M2<br />
VR<br />
Package C3 - Sleep<br />
(all core clocks<br />
gated)<br />
Fan<br />
~20%<br />
M2 M2 M2 M2 M2 M2<br />
VR<br />
Full bandwidth enabled<br />
From M1 state, memory can be put in self-refresh mode to enter the M2 state, further<br />
reducing memory power.<br />
Intel ® <strong>Xeon</strong> <strong>Phi</strong> <strong>Coprocessor</strong> <strong>Datasheet</strong><br />
56<br />
Document ID Number: 328209 003EN
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