Xeon-Phi-Coprocessor-Datasheet

Table 6-16.
Set Fan PWM Adder Command Response Format
Byte # Value Description
0 0x?? • Compcode
• 0x00 - Normal
• 0xc9 - Parameter out of range
6.6.3.7.2 OEM Get POST Register
The Get POST Register command allows the BMC to obtain the last POST code written
to the SMC by the coprocessor. The SMC does not modify this value in any way.
Table 6-17.
Get POST Register Request Format
Byte # Value Description
Command 0x04 • OEM Get POST Register
NetFn 0x3e • NETFN_OEM
Table 6-18.
Get POST Register Response Format
Byte # Value Description
0 0x?? • Compcode
• 0x00 - Normal
1-4 0x?? • 32 bit POST code in little endian format
6.6.3.7.3 OEM Assert Forced Throttle
The Assert Forced Throttle command allows the BMC to cause the SMC to assert the
PROCHOT pin to the coprocessor.
Table 6-19.
Assert Forced Throttle Request Format
Byte # Value Description
Command 0x05 • OEM Assert Forced Throttle
NetFn 0x3e • NETFN_OEM
0 0x?? • 0 = Deassert forced throttle
• 1 - Assert forced throttle
• All other values are reserved
Table 6-20.
Assert Forced Throttle Response Format
Byte # Value Description
0 0x?? • Compcode
• 0x00 - Normal
6.6.3.7.4 OEM Enable External Throttle
The Enable External Throttle command causes the SMC to enable a pin on the
baseboard connector (pin B12) allowing the baseboard BMC to directly assert the
PROCHOT signal. The baseboard requirements to enable this pin on the baseboard are
described in section 4.1.1. The signal to assert emergency throttling via pin B12 is
active low on the baseboard and is driven by the BMC. However, the pin must first be
enabled by the SMC. This can be accomplished by sending the Enable External Throttle
command as described in this section. The pin will need to be enabled each time a reset
or power cycle event occurs. Its state is not persistent across these events.
Intel ® Xeon Phi Coprocessor Datasheet
74
Document ID Number: 328209 003EN