The Microcontroller Idea Book - Jan Axelson's Lakeview Research

Powering Up
Figure 3-2. Truth tables for the 74HCT138 decoder and 74HCT373 octal
transparent latch.
A latch-enable input (LE) controls whether the outputs are latched (stored), or not latched
(immediately follow the inputs). Figure 3-2 shows the truth table for the chip. When pin 11
is high, 1Q-8Q follow 1D-8D. When pin 11 goes low, outputs 1Q-8Q will not change until pin
11 goes high again.
During each external memory access, 1Q-8Q store the low address byte, so the eight lines
that connect to these outputs carry the label LOW ADDRESS BUS. AND gate U3B latches, or
stores, U4’s outputs only when both ALE and ALEDIS are high. During normal memory
accesses, ALEDIS remains high, and ALE controls U4. ALEDIS disables the latches when
BASIC-52 executes its programming commands. Figure 3-1’s circuit doesn’t use the
programming commands, so ALE could control U4 directly, but again, I’ve included U3B
for future use.
Because AD0-AD7 hold the data to be read or written during a memory access, the signals as
a group carry the label DATA BUS. Each line of AD0-AD7 has a 10K pullup resistor. These are
The Microcontroller Idea Book 27