R4300i Product Information - MIPS Technologies, Inc.

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R4300i MICROPROCESSOR Converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual address in the TLB; there is a match when the virtual page number (VPN) of the address is the same as the VPN field of the entry, and either: • the Global (G) bit of the TLB entry is set, or • the ASID field of the virtual address is the same as the ASID field of the TLB entry. This match is referred to as a TLB hit. If there is no match, a TLB Miss exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual/physical addresses in memory. If there is a virtual address match in the TLB, the physical address is output from the TLB and concatenated with the Offset, which represents an address within the page frame space. Figure 44 shows the virtual-to-physical address translation of a 32-bit mode address. 39 39 ASID 8 Bits 31, 30 and 29 of the virtual address select user, supervisor, or kernel address spaces. Virtual Address with 1M (2 20 ) 4-Kbyte pages 3231 2928 20 bits = 1M pages 12 11 0 Virtual-to-physical translation in TLB TLB VPN Offset 20 12 Virtual-to-physical translation in TLB TLB 32-bit Physical Address 3231 2928 24 23 0 ASID VPN Offset 8 8 24 8 bits = 256 pages Virtual Address with 256 (2 8 )16-Mbyte pages Offset passed unchanged to physical memory 31 0 PFN Offset Offset passed unchanged to physical memory Figure 44 32-Bit-Mode Virtual Address Translation • The top portion of Figure 44 shows a virtual address with a 12-bit, or 4-Kbyte, page size, labelled Offset. The remaining 20 bits of the address represent the VPN, and index the 1M-entry page table. • The bottom portion of Figure 44 shows a virtual address with a 24-bit, or 16-Mbyte, page size, labelled Offset. The remaining 8 bits of the address represent the VPN, and index the 256-entry page table. Figure 45 shows the virtual-to-physical-address translation of a 64-bit mode address. This figure illustrates the two possible page sizes: a 4-Kbyte page (12 bits) and a 16-Mbyte page (24 bits). • The top portion of Figure 45 shows a virtual address with a 12-bit, or 4-Kbyte, page size, labelled Offset. The remaining 28 bits of the address represent the VPN, and index the 256M-entry page table. • The bottom portion of Figure 45 shows a virtual address with a 24-bit, or 16-Mbyte, page size, labelled Offset. The remaining 16 bits of the address represent the VPN, and index the 64K-entry page table. Mapped Virtual Address with 256M (2 28 ) 4-Kbyte pages 71 64 63 62 61 40 39 28 bits = 256M pages 12 11 0 ASID 8 VPN Offset 71 64 63 62 61 40 39 24 23 0 ASID 0 or -1 VPN Offset 8 0 or -1 24 24 16 24 16 bits = 64K pages Virtual Address with 64K (2 16 )16-Mbyte pages 28 Virtual-to-physical TLB translation in TLB 31 0 PFN Offset TLB Virtual-to-physical translation in TLB Figure 45 64-Bit-Mode Virtual Address Translation The processor has three operating modes that function in both 32- and 64-bit operations: User mode, Supervisor mode, and Kernel mode. The address space for each mode of operation are described in the following sections. In User mode, a single, uniform virtual address space—labelled User segment—is available; its size is: • 2 Gbytes (2 31 bytes) in 32-bit mode (useg) • 1 Tbyte (2 40 bytes) in 64-bit mode (xuseg) The User segment starts at address 0 and the current active user process resides in either useg (in 32-bit mode) or xuseg (in 64-bit mode). The TLB identically maps all references to useg/xuseg from all modes, and controls cache accessibility * . Figure 46 shows User mode virtual address space. 12 32-bit Physical Address Offset passed unchanged to physical memory Offset passed unchanged physical memory * The cached (C) field in a TLB entry determines whether the reference is cached; see Figure 20. 16 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR 0x FFFF FFFF 0x 8000 0000 0x 0000 0000 32-bit Address Error 2 GB Mapped Figure 46 User Mode Virtual Address Space The processor operates in User mode when the Status register contains the following bit-values: • KSU bits = 10 2 • EXL= 0 • ERL= 0 In conjunction with these bits, the UX bit in the Status register selects between 32- or 64-bit User mode addressing as follows: • when UX = 0, 32-bit useg space is selected • when UX = 1, 64-bit xuseg space is selected Supervisor mode is designed for layered operating systems in which a true kernel runs in R4300i Kernel mode, and the rest of the operating system runs in Supervisor mode. Figure 47 shows Supervisor mode address space. 32-bit 0x FFFF FFFF Address 0x E000 0000 error 0.5 GB 0x C000 0000 Mapped Address 0x A000 0000 error Address 0x 8000 0000 error 0x 0000 0000 2 GB Mapped Figure 47 Supervisor Mode Virtual Address Space The processor operates in Supervisor mode when the Status register contains the following bit-values: • KSU= 01 2 • EXL= 0 • ERL= 0 useg sseg suseg 0x FFFF FFFF FFFF FFFF 0x 0000 0100 0000 0000 0x 0000 0000 0000 0000 64-bit Address Error 1 TB Mapped 64-bit 0x FFFF FFFF FFFF FFFF Address 0x FFFF FFFF E000 0000 error 0.5 GB 0x FFFF FFFF C000 0000 Mapped Address 0x 4000 0100 0000 0000 error 1 TB Mapped 0x 4000 0000 0000 0000 Address 0x 0000 0100 0000 0000 error 1 TB Mapped 0x 0000 0000 0000 0000 xuseg csseg xsseg xsuseg In conjunction with these bits, the SX bit in the Status register selects between 32- or 64-bit Supervisor mode addressing: • when SX = 0, 32-bit supervisor space is selected • when SX = 1, 64-bit supervisor space is selected The processor operates in Kernel mode when the Status register contains one of the following values: • KSU= 00 2 • EXL= 1 • ERL= 1 In conjunction with these bits, the KX bit in the Status register selects between 32- or 64-bit Kernel mode addressing: • when KX = 0, 32-bit kernel space is selected • when KX = 1, 64-bit kernel space is selected The processor enters Kernel mode whenever an exception is detected and it remains in Kernel mode until an Exception Return (ERET) instruction is executed. The ERET instruction restores the processor to the mode existing prior to the exception. Kernel mode virtual address space is divided into regions differentiated by the high-order bits of the virtual address, as shown in Figure 48. 32-bit* 0x FFFF FFFF 0.5 GB 0x E000 0000 Mapped 0.5 GB Mapped 0x C000 0000 0.5 GB Unmapped 0x A000 0000 Uncached 0.5 GB Unmapped 0x 8000 0000 Cached 0x 0000 0000 2 GB Mapped kseg3 ksseg kseg1 kseg0 kuseg 64-bit 0x FFFF FFFF FFFF FFFF 0.5 GB 0x FFFF FFFF E000 0000 Mapped 0.5 GB 0x FFFF FFFF C000 0000 Mapped 0.5 GB Unmapped 0x FFFF FFFF A000 0000 Uncached 0.5 GB Unmapped 0x FFFF FFFF 8000 0000 Cacheable Address 0x C000 00FF 8000 0000 error Mapped 0x C000 0000 0000 0000 Address 0x 9800 0002 0000 0000 error Unmapped 0x 9800 0000 0000 0000 Cached Address 0x 9000 0002 0000 0000 error Unmapped 0x 9000 0000 0000 0000 Uncached Address 0x 4000 0100 0000 0000 error 1 TB 0x 4000 0000 0000 0000 Mapped Address 0x 0000 0100 0000 0000 error 1 TB 0x 0000 0000 0000 0000 Mapped Figure 48 Kernel Mode Virtual Address Space ckseg3 cksseg ckseg1 ckseg0 xkseg xkphys xkphys xksseg xkuseg 17 R4300 Data Sheet, Rev 0.3, April 1997
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R4300i Product Information - MIPS Technologies, Inc.

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