Rev. 1.11 - UBiio

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Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM Abbreviation I O I/O AI PWR GND NC Description Standard input-only ball. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected TABLE 10 Abbreviations for Ball Type Abbreviation SSTL LV-CMOS CMOS OD Description TABLE 11 Abbreviations for Buffer Type Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Rev. 1.11, 2007-07 12 11172006-LBIU-F1TN
Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM FIGURE 1 Chip Configuration for ×4 components, PG-TFBGA-60 (top view) Notes 1. V DDL and V SSDL are power and ground for the DLL. V DDL is connected to V DD on the device. V DD , V DDQ , V SSDL , V SS , and V SSQ are isolated on the device. 2. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit Rev. 1.11, 2007-07 13 11172006-LBIU-F1TN
Page 1 and 2: July 2007 HY[B/I]18T256400B[C/F](L)
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Page 43 and 44: Internet Data Sheet 7 Timing Charac
Page 59 and 60: Internet Data Sheet 7.3 Jitter Defi
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Internet Data Sheet 8 Package Dimen
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Internet Data Sheet 9 Product Nomen
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Internet Data Sheet HY[B/I]18T256[4
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Internet Data Sheet HY[B/I]18T256[4
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Internet Data Sheet Edition 2007-07
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Rev. 1.11 - UBiio

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