Rev. 1.11 - UBiio

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Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM Field Description Values Coding 11 Speed Grade –1.9 DDR2–1066 –25F DDR2–800 5–5–5 –2.5 DDR2–800 6–6–6 –3 DDR2–667 4–4–4 –3S DDR2–667 5–5–5 –3.7 DDR2–533 4–4–4 –5 DDR2–400 3–3–3 Rev. 1.11, 2007-07 66 11172006-LBIU-F1TN
Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM List of Figures Figure 1 Chip Configuration for ×4 components, PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2 Chip Configuration for ×8 components, PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3 Ball Configuration for ×16 components, PG-TFBGA-84 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4 Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 5 Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 6 AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 7 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 8 Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 9 Differential input waveform timing - t DS and t DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 10 Differential input waveform timing - t lS and t lH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 11 Package Outline P(G)-TFBGA-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 12 Package Outline P(G)-TFBGA-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Rev. 1.11, 2007-07 67 11172006-LBIU-F1TN
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Internet Data Sheet HY[B/I]18T256[4
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Page 59 and 60: Internet Data Sheet 7.3 Jitter Defi
Page 63 and 64: Internet Data Sheet 8 Package Dimen
Page 65: Internet Data Sheet 9 Product Nomen
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Rev. 1.11 - UBiio

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