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Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM 6 Specifications and Conditions This chapter describes the Specifications and Conditions. TABLE 45 I DD Measurement Conditions Parameter Symbol Note I DD0 1)2)3)4) Operating Current - One bank Active - Precharge t CK = t CK(IDD) , t RC = t RC(IDD) , t RAS = t RAS.MIN(IDD) , CKE is HIGH, CS is HIGH between valid commands. Address 5)6) and control inputs are switching; Databus inputs are switching. Operating Current - One bank Active - Read - Precharge I DD1 1)2)3)4)5 I OUT = 0 mA, BL = 4, t CK = t CK(IDD) , t RC = t RC(IDD) , t RAS = t RAS.MIN(IDD) , t RCD = t RCD(IDD) , AL = 0, CL = CL(IDD); )6) CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. Precharge Power-Down Current I DD2P 1)2)3)4)5 floating . All banks idle; CKE is LOW; t CK = t CK(IDD) ;Other control and address inputs are stable; Data bus inputs are )6) Precharge Standby Current I DD2N 1)2)3)4)5 Data bus inputs are switching . All banks idle; CS is HIGH; CKE is HIGH; t CK = t CK(IDD) ; Other control and address inputs are switching, )6) Precharge Quiet Standby Current I DD2Q 1)2)3)4)5 All banks idle; CS is HIGH; CKE is HIGH; t CK = t CK(IDD) ; Other control and address inputs are stable, Data )6) bus inputs are floating. Active Power-Down Current I DD3P(0) 1)2)3)4)5 All banks open; t CK = t CK(IDD) , CKE is LOW; Other control and address inputs are stable; Data bus inputs )6) are floating. MRS A12 bit is set to “0” (Fast Power-down Exit). Active Power-Down Current I DD3P(1) 1)2)3)4)5 All banks open; t CK = t CK(IDD) , CKE is LOW; Other control and address inputs are stable, Data bus inputs )6) are floating. MRS A12 bit is set to 1 (Slow Power-down Exit); Active Standby Current I DD3N 1)2)3)4)5 All banks open; t CK = t CK(IDD) ; t RAS = t RAS.MAX(IDD) , t RP = t RP(IDD) ; CKE is HIGH, CS is HIGH between valid )6) commands. Address inputs are switching; Data Bus inputs are switching; Operating Current I DD4R 1)2)3)4)5 Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL (IDD) ; t CK = t CK(IDD) ; t RAS = )6) t RAS.MAX.(IDD) , t RP = t RP(IDD) ; CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; I OUT = 0 mA. Operating Current I DD4W 1)2)3)4)5 Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL (IDD) ; t CK = t CK(IDD) ; t RAS = )6) t RAS.MAX(IDD) , t RP = t RP(IDD) ; CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Burst Refresh Current I DD5B 1)2)3)4)5 t CK = t CK(IDD) , Refresh command every t RFC = t RFC(IDD) interval, CKE is HIGH, CS is HIGH between valid )6) commands, Other control and address inputs are switching, Data bus inputs are switching. Distributed Refresh Current I DD5D 1)2)3)4)5 t CK = t CK(IDD) , Refresh command every t REFI = 7.8 μs interval, CKE is LOW and CS is HIGH between valid )6) commands, Other control and address inputs are switching, Data bus inputs are switching. Rev. 1.11, 2007-07 40 11172006-LBIU-F1TN
Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM Parameter Symbol Note Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current 1. All banks interleaving reads, I OUT = 0 mA; BL = 4, CL = CL (IDD) , AL = t RCD(IDD) -1 × t CK(IDD) ; t CK = t CK(IDD) , t RC = t RC(IDD) , t RRD = t RRD(IDD) ; CKE is HIGH, CS is HIGH between valid commands. Address bus inputs are stable during deselects; Data bus is switching. 2. Timing pattern: DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks) DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks) DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks) DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks) DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks) DDR2-800-666: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D(23 clocks) 1) V DDQ = 1.8 V ± 0.1 V; V DD = 1.8 V ± 0.1 V 2) I DD specifications are tested after the device is properly initialized. 3) I DD parameter are specified with ODT disabled. 4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. 5) Definitions for I DD : see Table 46 6) Timing parameter minimum and maximum values for I DD current measurements are defined in chapter 7.. 7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT 1)2)3)4)5 I DD6 )6) 1)2)3)4)5 I DD7 )6)7) Parameter Description TABLE 46 Definition for I DD LOW defined as V IN ≤ V IL(ac).MAX HIGH defined as V IN ≥ V IH(ac).MIN STABLE defined as inputs are stable at a HIGH or LOW level FLOATING defined as inputs are V REF = V DDQ / 2 SWITCHING defined as: Inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for DQ signals not including mask or strobes Rev. 1.11, 2007-07 41 11172006-LBIU-F1TN
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