Rev. 1.11 - UBiio

Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Parameter Symbol DDR2–533 Unit Notes 1)2)3)4)5)
Average periodic refresh Interval t REFI — 7.8 μs
Average periodic refresh Interval t REFI — 3.9 μs
15)17)
Auto-Refresh to Active/Auto-Refresh t RFC 75 — ns
16)
command period
Precharge-All (4 banks) command period t RP t RP — ns
Read preamble t RPRE 0.9 1.1 t CK
13)
Read postamble t RPST 0.40 0.60 t CK
13)
Active bank A to Active bank B command t RRD 7.5 — ns
13)17)
period
Active bank A to Active bank B command t RRD 10 — ns
15)21)
period
Internal Read to Precharge command delay t RTP 7.5 — ns
Write preamble t WPRE 0.25 — t CK
Write postamble t WPST 0.40 0.60 t CK
18)
Write recovery time for write without Auto- t WR 15 — ns
Precharge
Internal Write to Read command delay t WTR 7.5 — ns
19)
Exit power down to any valid command t XARD 2 — t CK
20)
(other than NOP or Deselect)
Exit active power-down mode to Read t XARDS 6 – AL — t CK
20)
command (slow exit, lower power)
Exit precharge power-down to any valid t XP 2 — t CK
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command t XSNR t RFC +10 — ns
Exit Self-Refresh to Read command t XSRD 200 — t CK
Write recovery time for write with Auto-
Precharge
WR t WR /t CK t CK
21)
1) V DDQ = 1.8 V ± 0.1 V; V DD = 1.8 V ±0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8 of this
datasheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined in Chapter 8.3 of this datasheet.
5) Inputs are not recognized as valid until V REF stabilizes. During the period before V REF stabilizes, CKE = 0.2 x V DDQ is recognized as low.
6) The output timing reference voltage level is V TT . See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. t CK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (t CL , t CH ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for t CL and t CH ).
Min.
Max.
6)
13)14)
Rev. 1.11, 2007-07 55
11172006-LBIU-F1TN