Rev. 1.11 - UBiio

Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
2.3 256-Mbit DDR2 Addressing
This chapter describes the 256-Mbit DDR2 addressing.
Configuration 64Mb x 4 1)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2 colbits × org/8 [Bytes]
TABLE 15
DDR2 Addressing for ×4 Organization
Bank Address
BA[1:0]
Number of Banks 4
Auto-Precharge
A10 / AP
Row Address
A[12:0]
Column Address
A11, A[9:0]
Number of Column Address Bits 11
2)
Number of I/Os 4
Page Size [Bytes] 1024 (1K)
3)
Note
Configuration 32Mb x 8 1)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2 colbits × org/8 [Bytes]
TABLE 16
DDR2 Addressing for ×8 Organization
Bank Address
BA[1:0]
Number of Banks 4
Auto-Precharge
A10 / AP
Row Address
A[12:0]
Column Address
A[9:0]
Number of Column Address Bits 10
2)
Number of I/Os 8
Page Size [Bytes] 1024 (1K)
3)
Note
TABLE 17
DDR2 Addressing for ×16 Organization
Configuration 16Mb x 16 1) Note
Bank Address
BA[1:0]
Number of Banks 4
Auto-Precharge
A10 / AP
Row Address
A[12:0]
Rev. 1.11, 2007-07 19
11172006-LBIU-F1TN