Rev. 1.11 - UBiio

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Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM 12) The t HZ , t RPST and t LZ , t RPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (t HZ, t RPST ), or begins driving (t LZ, t RPRE ). t HZ and t LZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 14) 0 °C≤ T CASE ≤ 85 °C 15) 85 °C < T CASE ≤ 95 °C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The t RRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for Lead-Free Products (RoHS Compliant)” on Page 6. 18) The maximum limit for the t WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) Minimum t WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing t XARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow power-down exit timing t XARDS has to be satisfied. 21) WR must be programmed to fulfill the minimum requirement for the t WR timing parameter, where WR MIN [cycles] = t WR (ns)/t CK (ns) rounded up to the next integer value. t DAL = WR + (t RP /t CK ). For each of the terms, if not already an integer, round to the next highest integer. t CK refers to the application clock period. WR refers to the WR parameter stored in the MRS. TABLE 55 DRAM Component Timing Parameter by Speed Grade - DDR2-400 Parameter Symbol DDR2–400 Unit Notes 1)2)3)4)5) DQ output access time from CK / CK t AC –600 +600 ps CAS A to CAS B command period t CCD 2 — t CK CK, CK high-level width t CH 0.45 0.55 t CK CKE minimum high and low pulse width t CKE 3 — t CK CK, CK low-level width t CL 0.45 0.55 t CK Auto-Precharge write recovery + precharge t DAL WR + t RP — t CK 7)20) time Minimum time clocks remain ON after CKE t DELAY t IS + t CK + t IH –– ns 8) asynchronously drops LOW DQ and DM input hold time (differential data t DH (base) 275 –– ps 9) strobe) DQ and DM input hold time (single ended data t DH1 (base) –25 — ps 10) strobe) DQ and DM input pulse width (each input) t DIPW 0.35 — t CK DQS output access time from CK / CK t DQSCK –500 +500 ps DQS input low (high) pulse width (write cycle) t DQSL,H 0.35 — t CK DQS-DQ skew (for DQS & associated DQ signals) t DQSQ — 350 ps 10) Min. Max. 6) Write command to 1st DQS latching transition t DQSS – 0.25 + 0.25 t CK DQ and DM input setup time (differential data strobe) t DS (base) 150 — ps DQ and DM input setup time (single ended t DS1 (base) –25 — ps data strobe) 10) 10) Rev. 1.11, 2007-07 56 11172006-LBIU-F1TN
Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM Parameter Symbol DDR2–400 Unit Notes 1)2)3)4)5) DQS falling edge hold time from CK (write cycle) Min. Max. t DSH 0.2 — t CK 6) DQS falling edge to CK setup time (write cycle) t DSS 0.2 — t CK Clock half period t HP MIN. (t CL, t CH ) Data-out high-impedance time from CK / CK t HZ — t AC.MAX ps Address and control input hold time t IH (base) 475 — ps Address and control input pulse width t IPW 0.6 — t CK (each input) Address and control input setup time t IS (base) 350 — ps DQ low-impedance time from CK / CK t LZ(DQ) 2 × t AC.MIN t AC.MAX ps DQS low-impedance from CK / CK t LZ(DQS) t AC.MIN t AC.MAX ps MRS command to ODT update delay t MOD 0 12 ns 11) 12) 10) 10) 13) 13) Mode register set command cycle time t MRD 2 — t CK OCD drive mode output delay t OIT 0 12 ns Data output hold time from DQS t QH t HP –t QHS — Data hold skew factor t QHS — 450 ps Average periodic refresh Interval t REFI — 7.8 μs Average periodic refresh Interval t REFI — 3.9 μs Auto-Refresh to Active/Auto-Refresh t RFC 75 — ns 16) command period Precharge-All (4 banks) command period t RP t RP — ns Read preamble t RPRE 0.9 1.1 t CK 13) Read postamble t RPST 0.40 0.60 t CK 13) Active bank A to Active bank B command t RRD 7.5 — ns 13)17) period Active bank A to Active bank B command t RRD 10 — ns 15)21) period Internal Read to Precharge command delay t RTP 7.5 — ns Write preamble t WPRE 0.25 — t CK Write postamble t WPST 0.40 0.60 t CK 18) Write recovery time for write without Auto- t WR 15 — ns Precharge Internal Write to Read command delay t WTR 10 — ns 19) Exit power down to any valid command t XARD 2 — t CK 20) (other than NOP or Deselect) Exit active power-down mode to Read t XARDS 6 – AL — t CK 20) command (slow exit, lower power) Exit precharge power-down to any valid t XP 2 — t CK command (other than NOP or Deselect) Exit Self-Refresh to non-Read command t XSNR t RFC +10 — ns 13)14) 15)17) Rev. 1.11, 2007-07 57 11172006-LBIU-F1TN
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July 2007 HY[B/I]18T256400B[C/F](L)
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Rev. 1.11 - UBiio

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